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Impact of back biasing on carrier transport in ultra-thin-body and BOX (UTBB) Fully Depleted SOI MOSFETs

2012 Symposium on VLSI Technology (VLSIT), 2012, p.113-114

2012

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IEEE_Xplore

Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors

ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC), 2021, p.223-226

2021

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New insight on the geometry dependence of BTI in 3D technologies based on experiments and modeling

2017 Symposium on VLSI Technology, 2017, p.T134-T135

2017

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Effect of measurement speed (μs-800 ps) on the characterization of reliability behaviors for FDSOI nMOSFETs

2018 IEEE International Reliability Physics Symposium (IRPS), 2018, p.6E.6-1-6E.6-6

2018

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IEEE_Xplore

Analog performance of strained SOI nanowires down to 10K

2016 46th European Solid-State Device Research Conference (ESSDERC), 2016, p.222-225

2016

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IEEE_Xplore

Opportunities brought by sequential 3D CoolCube™ integration

2016 46th European Solid-State Device Research Conference (ESSDERC), 2016, p.226-229

2016

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IEEE_Xplore

4-port RF performance assessment and compact modeling of UTBB-FDSOI transistors

2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015, p.355-358

2015

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Low-field Mobility Degradation Factors Temperature Dependence in Two-level Stacked Nanowire MOSFETs from 120K to 400K

2023 37th Symposium on Microelectronics Technology and Devices (SBMicro), 2023, p.1-4

2023

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Electrical Characterization of Ω-Gate Nanowire MOSFETs Down to Cryogenic Temperatures

2023 37th Symposium on Microelectronics Technology and Devices (SBMicro), 2023, p.1-4

2023

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A wigner function-based determinist method for the simulation of quantum transport in silicon nanowire transistors

2011 International Conference on Simulation of Semiconductor Processes and Devices, 2011, p.75-78

2011

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IEEE_Xplore

Extraction of Drain Current Variability Components in Junctionless Nanowire Transistors

2023 International Conference on Noise and Fluctuations (ICNF), 2023, p.1-4

2023

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Experimental comparison of programming mechanisms in 1T-DRAM cells with variable channel length

2010 Proceedings of the European Solid State Device Research Conference, 2010, p.150-153

2010

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IEEE_Xplore

Experimental Comparison of Junctionless and Inversion-Mode Nanowire MOSFETs Electrical Properties at High Temperatures

2022 36th Symposium on Microelectronics Technology (SBMICRO), 2022, p.1-4

2022

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Analysis of the Gate-Induced Drain Leakage of SOI Nanowire and Nanosheet MOS Transistors at High Temperatures

2022 IEEE Latin American Electron Devices Conference (LAEDC), 2022, p.1-4

2022

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Disruptive approaches towards Energy Efficient VLSI Technologies

2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT), 2023, p.1-2

2023

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Analysis of Variability in Transconductance and Mobility of Nanowire Transistors

2022 36th Symposium on Microelectronics Technology (SBMICRO), 2022, p.1-4

2022

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Stress-induced performance enhancement in Si ultra-thin body FD-SOI MOSFETs: Impacts of scaling

2011 Symposium on VLSI Technology - Digest of Technical Papers, 2011, p.162-163

2011

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IEEE_Xplore

Evaluation of Analog Characteristics of n-Type Vertically Stacked Nanowires

2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2020, p.1-4

2020

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IEEE_Xplore

An Experimental Evaluation of Fin Width and Low-Temperature Influence on GIDL in Stacked SOI Nanowires

2022 IEEE 15th Workshop on Low Temperature Electronics (WOLTE), 2022, p.1-4

2022

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Performance of Stacked SOI Nanowires in a Wide Temperature Range

2021 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS), 2021, p.1-4

2021

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IEEE_Xplore

Temperature Influence on the Electrical Properties of Vertically Stacked Nanowire MOSFETs

2021 35th Symposium on Microelectronics Technology and Devices (SBMicro), 2021, p.1-4

2021

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Extraction of the Back Channel Mobility in SOI Nanowire MOS Transistors under Substrate Biasing

2022 IEEE Latin American Electron Devices Conference (LAEDC), 2022, p.1-4

2022

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Study and Optimization of Silicon-CVD Diamond Interface for SOD Applications

MRS proceedings, 2009, Vol.1203 (1), Article 1203-J04-01

2009

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Back bias impact on effective mobility of p-type nanowire SOI MOSFETs

2018 33rd Symposium on Microelectronics Technology and Devices (SBMicro), 2018, p.1-4

2018

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IEEE_Xplore

Impact of substrate bias on the mobility of n-type ɷ-gate SOI nanowire MOSFETs

2019 34th Symposium on Microelectronics Technology and Devices (SBMicro), 2019, p.1-4

2019

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Impact of back biasing on carrier transport in ultra-thin-body and BOX (UTBB) Fully Depleted SOI MOSFETs

Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors

New insight on the geometry dependence of BTI in 3D technologies based on experiments and modeling

Effect of measurement speed (μs-800 ps) on the characterization of reliability behaviors for FDSOI nMOSFETs

Analog performance of strained SOI nanowires down to 10K

Opportunities brought by sequential 3D CoolCube™ integration

4-port RF performance assessment and compact modeling of UTBB-FDSOI transistors

Low-field Mobility Degradation Factors Temperature Dependence in Two-level Stacked Nanowire MOSFETs from 120K to 400K

Electrical Characterization of Ω-Gate Nanowire MOSFETs Down to Cryogenic Temperatures

A wigner function-based determinist method for the simulation of quantum transport in silicon nanowire transistors

Extraction of Drain Current Variability Components in Junctionless Nanowire Transistors

Experimental comparison of programming mechanisms in 1T-DRAM cells with variable channel length

Experimental Comparison of Junctionless and Inversion-Mode Nanowire MOSFETs Electrical Properties at High Temperatures

Analysis of the Gate-Induced Drain Leakage of SOI Nanowire and Nanosheet MOS Transistors at High Temperatures

Disruptive approaches towards Energy Efficient VLSI Technologies

Analysis of Variability in Transconductance and Mobility of Nanowire Transistors

Stress-induced performance enhancement in Si ultra-thin body FD-SOI MOSFETs: Impacts of scaling

Evaluation of Analog Characteristics of n-Type Vertically Stacked Nanowires

An Experimental Evaluation of Fin Width and Low-Temperature Influence on GIDL in Stacked SOI Nanowires

Performance of Stacked SOI Nanowires in a Wide Temperature Range

Temperature Influence on the Electrical Properties of Vertically Stacked Nanowire MOSFETs

Extraction of the Back Channel Mobility in SOI Nanowire MOS Transistors under Substrate Biasing

Study and Optimization of Silicon-CVD Diamond Interface for SOD Applications

Back bias impact on effective mobility of p-type nanowire SOI MOSFETs

Impact of substrate bias on the mobility of n-type ɷ-gate SOI nanowire MOSFETs

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