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An 18.8-to-23.3 GHz ADPLL Based on Charge-Steering-Sampling Technique Achieving 75.9 fs RMS Jitter and -252 dB FoM

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023, p.1-2

2023

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All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

IPSJ Transactions on System LSI Design Methodology, 2014, Vol.7, pp.2-15

2014

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A 25.4-27.5 GHz Ping-Pong Charge-Sharing Locking PLL Achieving 42 fs Jitter with Implicit Reference Frequency Doubling

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2

2024

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A 9-GHz Subsampling-Chopper PLL with Charge-Share Cancelling and Achieving 57.8-fs-rms Jitter with 15dB In-Band Noise Improvement

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2

2024

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A 24-dBm Tri-Stacked House-of-Cards Doherty Polar Transmitter for NB-IoT with Digital PLL Phase Modulator

2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 2024, p.440-443

2024

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A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur

2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, Vol.65, p.1-3

2022

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A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs

2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, Vol.65, p.380-382

2022

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Time-Domain Modeling of a Phase-Domain All-Digital Phase-Locked Loop for RF Applications

2007 IEEE Custom Integrated Circuits Conference, 2007, p.861-864

2007

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A 60 GHz 25% tuning range frequency generator with implicit divider based on third harmonic extraction with 182 dBc/Hz FoM

2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015, p.279-282

2015

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17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and −250dB FoM

2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020, p.276-278

2020

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Gain Estimation of a Digital-to-Time Converter for Phase-Prediction All-Digital PLL

2013 European Conference on Circuit Theory and Design (ECCTD), 2013, p.1-4

2013

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A low-power all-digital PLL architecture based on phase prediction

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012), 2012, p.797-800

2012

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A 56.4-to-63.4GHz spurious-free all-digital fractional-N PLL in 65nm CMOS

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 2013, p.352-353

2013

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A 3.5-6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise

ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016, p.209-212

2016

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A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.448-450

2018

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Fractional spur suppression in all-digital phase-locked loops

2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015, p.2565-2568

2015

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A fully integrated 28nm Bluetooth Low-Energy transmitter with 36% system efficiency at 3dBm

ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC), 2015, p.356-359

2015

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An all-digital offset PLL architecture

2010 IEEE Radio Frequency Integrated Circuits Symposium, 2010, p.17-20

2010

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State-of-the-art and future directions of high-performance all-digital frequency synthesis in nanometer CMOS

2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, p.229-232

Staszewski, R B

2010

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All-digital PLL and GSM/EDGE transmitter in 90nm CMOS

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005, 2005, p.316-600 Vol. 1

2005

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A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS

2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015, p.2289-2292

2015

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Spur-free all-digital PLL in 65nm for mobile phones

2011 IEEE International Solid-State Circuits Conference, 2011, p.52-54

2011

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9.8 An 860μW 2.1-to-2.7GHz all-digital PLL-based frequency modulator with a DTC-assisted snapshot TDC for WPAN (Bluetooth Smart and ZigBee) applications

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014, p.172-173

2014

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A mm-Wave MIMO Transmitter with a Digital Beam Steering Capability Using CMOS All-Digital Phase-Locked Loop Chips

2018 IEEE MTT-S International Microwave Workshop Series on 5G Hardware and System Technologies (IMWS-5G), 2018, p.1-3

2018

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14.5 A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CM0S

2015 IEEE International Solid State Circuits Conference (ISSCC), 2015, p.1-3

2015

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An 18.8-to-23.3 GHz ADPLL Based on Charge-Steering-Sampling Technique Achieving 75.9 fs RMS Jitter and -252 dB FoM

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

A 25.4-27.5 GHz Ping-Pong Charge-Sharing Locking PLL Achieving 42 fs Jitter with Implicit Reference Frequency Doubling

A 9-GHz Subsampling-Chopper PLL with Charge-Share Cancelling and Achieving 57.8-fs-rms Jitter with 15dB In-Band Noise Improvement

A 24-dBm Tri-Stacked House-of-Cards Doherty Polar Transmitter for NB-IoT with Digital PLL Phase Modulator

A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur

A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs

Time-Domain Modeling of a Phase-Domain All-Digital Phase-Locked Loop for RF Applications

A 60 GHz 25% tuning range frequency generator with implicit divider based on third harmonic extraction with 182 dBc/Hz FoM

17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and −250dB FoM

Gain Estimation of a Digital-to-Time Converter for Phase-Prediction All-Digital PLL

A low-power all-digital PLL architecture based on phase prediction

A 56.4-to-63.4GHz spurious-free all-digital fractional-N PLL in 65nm CMOS

A 3.5-6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise

A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference

Fractional spur suppression in all-digital phase-locked loops

A fully integrated 28nm Bluetooth Low-Energy transmitter with 36% system efficiency at 3dBm

An all-digital offset PLL architecture

State-of-the-art and future directions of high-performance all-digital frequency synthesis in nanometer CMOS

All-digital PLL and GSM/EDGE transmitter in 90nm CMOS

A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS

Spur-free all-digital PLL in 65nm for mobile phones

9.8 An 860μW 2.1-to-2.7GHz all-digital PLL-based frequency modulator with a DTC-assisted snapshot TDC for WPAN (Bluetooth Smart and ZigBee) applications

A mm-Wave MIMO Transmitter with a Digital Beam Steering Capability Using CMOS All-Digital Phase-Locked Loop Chips

14.5 A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CM0S

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