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An 18.8-to-23.3 GHz ADPLL Based on Charge-Steering-Sampling Technique Achieving 75.9 fs RMS Jitter and -252 dB FoM

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023, p.1-2

2023

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Rapid Locking Range Analysis of a Sub-Harmonic ILO considering Injection Waveforms of Different Multiplied Ratios

2023 34th Irish Signals and Systems Conference (ISSC), 2023, p.1-4

2023

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A wideband 60 GHz class-E/F2 power amplifier in 40nm CMOS

2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015, p.215-218

2015

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A 25.4-27.5 GHz Ping-Pong Charge-Sharing Locking PLL Achieving 42 fs Jitter with Implicit Reference Frequency Doubling

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2

2024

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A 0.5V 0.5mW switching current source oscillator

2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015, p.183-186

2015

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A 0.3V, 35% Tuning-Range, 60kHz 1/f3-Corner Digitally Controlled Oscillator with Vertically Integrated Switched Capacitor Banks Achieving FoMT of -199dB in 28-nm CMOS

2019 IEEE Custom Integrated Circuits Conference (CICC), 2019, p.1-4

2019

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A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur

2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, Vol.65, p.1-3

2022

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25.4 A 1/f noise upconversion reduction technique applied to Class-D and Class-F oscillators

2015 IEEE International Solid State Circuits Conference (ISSCC), 2015, p.1-3

2015

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A 77/79-GHz Frequency Generator in 16-nm CMOS for FMCW Radar Applications Based on a 26-GHz Oscillator with Co-Generated Third Harmonic

ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC), 2019, p.53-56

2019

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A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.448-450

2018

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A fully integrated 28nm Bluetooth Low-Energy transmitter with 36% system efficiency at 3dBm

ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC), 2015, p.356-359

2015

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An all-digital offset PLL architecture

2010 IEEE Radio Frequency Integrated Circuits Symposium, 2010, p.17-20

2010

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19.6 A 0.2V trifilar-coil DCO with DC-DC converter in 16nm FinFET CMOS with 188dB FOM, 1.3kHz resolution, and frequency pushing of 38MHz/V for energy harvesting applications

2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, p.332-333

2017

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15.5 Cryo-CMOS circuits and systems for scalable quantum computing

2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, p.264-265

2017

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14.5 A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CM0S

2015 IEEE International Solid State Circuits Conference (ISSCC), 2015, p.1-3

2015

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Injection Spurs due to Reference Frequency Retiming by a Channel Dependent Clock at the ADPLL RF Output and its Mitigation

2007 IEEE International Symposium on Circuits and Systems (ISCAS), 2007, p.3291-3294

2007

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A 24-31 GHz Reference Oversampling ADPLL Achieving FoMjitter−N of -269.3 dB

2021 Symposium on VLSI Circuits, 2021, p.1-2

2021

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A study of RF oscillator reliability in nanoscale CMOS

2013 European Conference on Circuit Theory and Design (ECCTD), 2013, p.1-4

2013

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28 GHz Quadrature Frequency Generation Exploiting Injection-Locked Harmonic Extractors for 5G Communications

2019 17th IEEE International New Circuits and Systems Conference (NEWCAS), 2019, p.1-4

2019

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A 30-GHz class-F23 oscillator in 28nm CMOS using harmonic extraction and achieving 120 kHz 1/f3 corner

ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, 2017, p.87-90

2017

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TDC-based frequency synthesizer for wireless applications

2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers, 2004, p.215-218

2004

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Analog Path for Triple Band WCDMA Polar Modulated Transmitter in 90nm CMOS

2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2007, p.185-188

2007

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Harmonic characterization of mismatches in deep sub-micron varactors for a digitally controlled RF oscillator

48th Midwest Symposium on Circuits and Systems, 2005, 2005, p.951-954 Vol. 2

2005

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Characterization of deep-submicron varactor mismatches in a digitally controlled oscillator

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005, 2005, p.605-608

2005

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Quad Band Digitally Controlled Oscillator for WCDMA Transmitter in 90nm CMOS

IEEE Custom Integrated Circuits Conference 2006, 2006, p.129-132

2006

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An 18.8-to-23.3 GHz ADPLL Based on Charge-Steering-Sampling Technique Achieving 75.9 fs RMS Jitter and -252 dB FoM

Rapid Locking Range Analysis of a Sub-Harmonic ILO considering Injection Waveforms of Different Multiplied Ratios

A wideband 60 GHz class-E/F2 power amplifier in 40nm CMOS

A 25.4-27.5 GHz Ping-Pong Charge-Sharing Locking PLL Achieving 42 fs Jitter with Implicit Reference Frequency Doubling

A 0.5V 0.5mW switching current source oscillator

A 0.3V, 35% Tuning-Range, 60kHz 1/f3-Corner Digitally Controlled Oscillator with Vertically Integrated Switched Capacitor Banks Achieving FoMT of -199dB in 28-nm CMOS

A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur

25.4 A 1/f noise upconversion reduction technique applied to Class-D and Class-F oscillators

A 77/79-GHz Frequency Generator in 16-nm CMOS for FMCW Radar Applications Based on a 26-GHz Oscillator with Co-Generated Third Harmonic

A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference

A fully integrated 28nm Bluetooth Low-Energy transmitter with 36% system efficiency at 3dBm

An all-digital offset PLL architecture

19.6 A 0.2V trifilar-coil DCO with DC-DC converter in 16nm FinFET CMOS with 188dB FOM, 1.3kHz resolution, and frequency pushing of 38MHz/V for energy harvesting applications

15.5 Cryo-CMOS circuits and systems for scalable quantum computing

14.5 A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CM0S

Injection Spurs due to Reference Frequency Retiming by a Channel Dependent Clock at the ADPLL RF Output and its Mitigation

A 24-31 GHz Reference Oversampling ADPLL Achieving FoMjitter−N of -269.3 dB

A study of RF oscillator reliability in nanoscale CMOS

28 GHz Quadrature Frequency Generation Exploiting Injection-Locked Harmonic Extractors for 5G Communications

A 30-GHz class-F23 oscillator in 28nm CMOS using harmonic extraction and achieving 120 kHz 1/f3 corner

TDC-based frequency synthesizer for wireless applications

Analog Path for Triple Band WCDMA Polar Modulated Transmitter in 90nm CMOS

Harmonic characterization of mismatches in deep sub-micron varactors for a digitally controlled RF oscillator

Characterization of deep-submicron varactor mismatches in a digitally controlled oscillator

Quad Band Digitally Controlled Oscillator for WCDMA Transmitter in 90nm CMOS

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