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RF CMOS Oscillators for Modern Wireless Applications

1, 2019

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An 18.8-to-23.3 GHz ADPLL Based on Charge-Steering-Sampling Technique Achieving 75.9 fs RMS Jitter and -252 dB FoM

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023, p.1-2

2023

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All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

IPSJ Transactions on System LSI Design Methodology, 2014, Vol.7, pp.2-15

2014

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A wideband 60 GHz class-E/F2 power amplifier in 40nm CMOS

2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015, p.215-218

2015

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Cryo-CMOS for Quantum System On-Chip Integration: Quantum Computing as the Development Driver

IEEE solid state circuits magazine, 2021-01, Vol.13 (2), p.46-53

2021

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A 25.4-27.5 GHz Ping-Pong Charge-Sharing Locking PLL Achieving 42 fs Jitter with Implicit Reference Frequency Doubling

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2

2024

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All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

Information and Media Technologies, 2014, Vol.9(1), pp.1-14

2014

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Radio-Frequency Digital-to-Analog Converters

2016

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A 9-GHz Subsampling-Chopper PLL with Charge-Share Cancelling and Achieving 57.8-fs-rms Jitter with 15dB In-Band Noise Improvement

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2

2024

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A 50μW Ring-Type Complementary Inverse-Class-D Oscillator with 191.4dBc/Hz FoM and 205.6dBc/Hz FoMA

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023, p.1-2

2023

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Broadband Fully Integrated GaN Power Amplifier With Embedded Minimum Inductor Bandpass Filter and AM-PM Compensation

ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC), 2019, p.159-162

2019

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Discrete-time Receivers, from N-Path to Charge Sharing Band-pass Filters: a Comparison

Journal of Integrated Circuits and Systems, 2023-12, Vol.18 (3), p.1-10

2023

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A DPLL-Based Phase Modulator Achieving -46dB EVM with A Fast Two-Step DCO Nonlinearity Calibration and Non-Uniform Clock Compensation

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022, p.14-15

2022

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A 184.6-dBc/Hz FoM 100-kHz Flicker Phase Noise Corner 30-GHz Rotary Traveling-Wave Oscillator Using Distributed Stubs in 22-nm FD-SOI

ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC), 2019, p.103-106

2019

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A 0.3V, 35% Tuning-Range, 60kHz 1/f3-Corner Digitally Controlled Oscillator with Vertically Integrated Switched Capacitor Banks Achieving FoMT of -199dB in 28-nm CMOS

2019 IEEE Custom Integrated Circuits Conference (CICC), 2019, p.1-4

2019

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A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur

2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, Vol.65, p.1-3

2022

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A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs

2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, Vol.65, p.380-382

2022

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17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and −250dB FoM

2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020, p.276-278

2020

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SE3: Favorite Circuit Design and Testing Mistakes of Starting Engineers

2021 IEEE International Solid-State Circuits Conference (ISSCC), 2021, Vol.64, p.541-542

2021

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BJT Device and Circuit Co-Optimization Enabling Bandgap Reference and Temperature Sensing in 7-nm FinFET

2018 48th European Solid-State Device Research Conference (ESSDERC), 2018, p.86-89

2018

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Gain Estimation of a Digital-to-Time Converter for Phase-Prediction All-Digital PLL

2013 European Conference on Circuit Theory and Design (ECCTD), 2013, p.1-4

2013

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25.4 A 1/f noise upconversion reduction technique applied to Class-D and Class-F oscillators

2015 IEEE International Solid State Circuits Conference (ISSCC), 2015, p.1-3

2015

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A 103fsrms 1.32mW 50MS/s 1.25MHz bandwidth two-step flash-ΔΣ time-to-digital converter for ADPLL

2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015, p.95-98

2015

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3.8 A fully integrated highly reconfigurable discrete-time superheterodyne receiver

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014, p.1-3

2014

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30.8 A 3.5mm×3.8mm Crystal-Less MICS Transceiver Featuring Coverages of ±160ppm Carrier Frequency Offset and 4.8-VSWR Antenna Impedance for Insertable Smart Pills

2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020, p.474-476

2020

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RF CMOS Oscillators for Modern Wireless Applications

An 18.8-to-23.3 GHz ADPLL Based on Charge-Steering-Sampling Technique Achieving 75.9 fs RMS Jitter and -252 dB FoM

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

A wideband 60 GHz class-E/F2 power amplifier in 40nm CMOS

Cryo-CMOS for Quantum System On-Chip Integration: Quantum Computing as the Development Driver

A 25.4-27.5 GHz Ping-Pong Charge-Sharing Locking PLL Achieving 42 fs Jitter with Implicit Reference Frequency Doubling

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

Radio-Frequency Digital-to-Analog Converters

A 9-GHz Subsampling-Chopper PLL with Charge-Share Cancelling and Achieving 57.8-fs-rms Jitter with 15dB In-Band Noise Improvement

A 50μW Ring-Type Complementary Inverse-Class-D Oscillator with 191.4dBc/Hz FoM and 205.6dBc/Hz FoMA

Broadband Fully Integrated GaN Power Amplifier With Embedded Minimum Inductor Bandpass Filter and AM-PM Compensation

Discrete-time Receivers, from N-Path to Charge Sharing Band-pass Filters: a Comparison

A DPLL-Based Phase Modulator Achieving -46dB EVM with A Fast Two-Step DCO Nonlinearity Calibration and Non-Uniform Clock Compensation

A 184.6-dBc/Hz FoM 100-kHz Flicker Phase Noise Corner 30-GHz Rotary Traveling-Wave Oscillator Using Distributed Stubs in 22-nm FD-SOI

A 0.3V, 35% Tuning-Range, 60kHz 1/f3-Corner Digitally Controlled Oscillator with Vertically Integrated Switched Capacitor Banks Achieving FoMT of -199dB in 28-nm CMOS

A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur

A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs

17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and −250dB FoM

SE3: Favorite Circuit Design and Testing Mistakes of Starting Engineers

BJT Device and Circuit Co-Optimization Enabling Bandgap Reference and Temperature Sensing in 7-nm FinFET

Gain Estimation of a Digital-to-Time Converter for Phase-Prediction All-Digital PLL

25.4 A 1/f noise upconversion reduction technique applied to Class-D and Class-F oscillators

A 103fsrms 1.32mW 50MS/s 1.25MHz bandwidth two-step flash-ΔΣ time-to-digital converter for ADPLL

3.8 A fully integrated highly reconfigurable discrete-time superheterodyne receiver

30.8 A 3.5mm×3.8mm Crystal-Less MICS Transceiver Featuring Coverages of ±160ppm Carrier Frequency Offset and 4.8-VSWR Antenna Impedance for Insertable Smart Pills

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