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RF CMOS Oscillators for Modern Wireless Applications

1, 2019

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All-digital frequency synthesizer in deep-submicron CMOS

1st ed., 2006

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Multi-Mode / Multi-Band RF Transceivers for Wireless Communications: Advanced Techniques, Architectures, and Trends

1st ed., 2010

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Radio-Frequency Digital-to-Analog Converters: Implementation in Nanoscale CMOS

Morteza S Alavi, Jaimin Mehta, Robert Bogdan Staszewski

1, 2016

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All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

IPSJ Transactions on System LSI Design Methodology, 2014, Vol.7, pp.2-15

2014

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Rapid Locking Range Analysis of a Sub-Harmonic ILO considering Injection Waveforms of Different Multiplied Ratios

2023 34th Irish Signals and Systems Conference (ISSC), 2023, p.1-4

2023

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A wideband 60 GHz class-E/F2 power amplifier in 40nm CMOS

2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015, p.215-218

2015

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All-digital RF frequency modulation

2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011, p.426-429

Staszewski, Robert Bogdan

2011

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A 25.4-27.5 GHz Ping-Pong Charge-Sharing Locking PLL Achieving 42 fs Jitter with Implicit Reference Frequency Doubling

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2

2024

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All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

Information and Media Technologies, 2014, Vol.9(1), pp.1-14

2014

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Radio-Frequency Digital-to-Analog Converters

2016

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A 9-GHz Subsampling-Chopper PLL with Charge-Share Cancelling and Achieving 57.8-fs-rms Jitter with 15dB In-Band Noise Improvement

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2

2024

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A 50μW Ring-Type Complementary Inverse-Class-D Oscillator with 191.4dBc/Hz FoM and 205.6dBc/Hz FoMA

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023, p.1-2

2023

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Broadband Fully Integrated GaN Power Amplifier With Embedded Minimum Inductor Bandpass Filter and AM-PM Compensation

ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC), 2019, p.159-162

2019

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A DPLL-Based Phase Modulator Achieving -46dB EVM with A Fast Two-Step DCO Nonlinearity Calibration and Non-Uniform Clock Compensation

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022, p.14-15

2022

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A 0.5V 0.5mW switching current source oscillator

2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015, p.183-186

2015

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An impedance sensor for MEMS adaptive antenna matching

2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015, p.379-382

2015

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A 0.3V, 35% Tuning-Range, 60kHz 1/f3-Corner Digitally Controlled Oscillator with Vertically Integrated Switched Capacitor Banks Achieving FoMT of -199dB in 28-nm CMOS

2019 IEEE Custom Integrated Circuits Conference (CICC), 2019, p.1-4

2019

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A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur

2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, Vol.65, p.1-3

2022

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A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs

2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, Vol.65, p.380-382

2022

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Time-Domain Modeling of a Phase-Domain All-Digital Phase-Locked Loop for RF Applications

2007 IEEE Custom Integrated Circuits Conference, 2007, p.861-864

2007

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Third-harmonic injection technique applied to a 5.87-to-7.56GHz 65nm CMOS Class-F oscillator with 192dBc/Hz FOM

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 2013, p.348-349

2013

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17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and −250dB FoM

2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020, p.276-278

2020

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SE3: Favorite Circuit Design and Testing Mistakes of Starting Engineers

2021 IEEE International Solid-State Circuits Conference (ISSCC), 2021, Vol.64, p.541-542

2021

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BJT Device and Circuit Co-Optimization Enabling Bandgap Reference and Temperature Sensing in 7-nm FinFET

2018 48th European Solid-State Device Research Conference (ESSDERC), 2018, p.86-89

2018

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RF CMOS Oscillators for Modern Wireless Applications

All-digital frequency synthesizer in deep-submicron CMOS

Multi-Mode / Multi-Band RF Transceivers for Wireless Communications: Advanced Techniques, Architectures, and Trends

Radio-Frequency Digital-to-Analog Converters: Implementation in Nanoscale CMOS

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

Rapid Locking Range Analysis of a Sub-Harmonic ILO considering Injection Waveforms of Different Multiplied Ratios

A wideband 60 GHz class-E/F2 power amplifier in 40nm CMOS

All-digital RF frequency modulation

A 25.4-27.5 GHz Ping-Pong Charge-Sharing Locking PLL Achieving 42 fs Jitter with Implicit Reference Frequency Doubling

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

Radio-Frequency Digital-to-Analog Converters

A 9-GHz Subsampling-Chopper PLL with Charge-Share Cancelling and Achieving 57.8-fs-rms Jitter with 15dB In-Band Noise Improvement

A 50μW Ring-Type Complementary Inverse-Class-D Oscillator with 191.4dBc/Hz FoM and 205.6dBc/Hz FoMA

Broadband Fully Integrated GaN Power Amplifier With Embedded Minimum Inductor Bandpass Filter and AM-PM Compensation

A DPLL-Based Phase Modulator Achieving -46dB EVM with A Fast Two-Step DCO Nonlinearity Calibration and Non-Uniform Clock Compensation

A 0.5V 0.5mW switching current source oscillator

An impedance sensor for MEMS adaptive antenna matching

A 0.3V, 35% Tuning-Range, 60kHz 1/f3-Corner Digitally Controlled Oscillator with Vertically Integrated Switched Capacitor Banks Achieving FoMT of -199dB in 28-nm CMOS

A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur

A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs

Time-Domain Modeling of a Phase-Domain All-Digital Phase-Locked Loop for RF Applications

Third-harmonic injection technique applied to a 5.87-to-7.56GHz 65nm CMOS Class-F oscillator with 192dBc/Hz FOM

17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and −250dB FoM

SE3: Favorite Circuit Design and Testing Mistakes of Starting Engineers

BJT Device and Circuit Co-Optimization Enabling Bandgap Reference and Temperature Sensing in 7-nm FinFET

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