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HBDCA: A Toolchain for High-Accuracy BRAM-Defined CNN Accelerator on FPGA with Flexible Structure

IEICE Transactions on Information and Systems, 2021/10/01, Vol.E104.D(10), pp.1724-1733

2021

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A survey of FPGA design for AI era

Journal of semiconductors, 2020-02, Vol.41 (2), p.21402

2020

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FCA-BNN: Flexible and Configurable Accelerator for Binarized Neural Networks on FPGA

IEICE Transactions on Information and Systems, 2021/08/01, Vol.E104.D(8), pp.1367-1377

2021

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A high-performance reconfigurable VLSI architecture for vbsme in H.264

IEEE transactions on consumer electronics, 2008-08, Vol.54 (3), p.1338-1345

2008

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Effect of dispersion of nano-magnesium hydroxide on the flammability of flame retardant ternary composites

Composites science and technology, 2007-05, Vol.67 (6), p.974-980

2007

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Flame retardant synergism of rubber and Mg(OH) 2 in EVA composites

Polymer (Guilford), 2007-04, Vol.48 (9), p.2537-2541

2007

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A deep research on the chip verification platform based on network

2017 IEEE 12th International Conference on ASIC (ASICON), 2017, p.323-326

2017

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Application dependent FPGA interconnect test method with small test configuration number using SMT net-grouping constraints

IEICE Electronics Express, 2024, Article 21.20230495

2024

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EdgeMedNet: Lightweight and Accurate U-Net for Implementing Efficient Medical Image Segmentation on Edge Devices

IEEE transactions on circuits and systems. II, Express briefs, 2023-12, Vol.70 (12), p.1-1

2023

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Flame retardant nanocomposites of polyamide 6/clay/silicone rubber with high toughness and good flowability

Polymer (Guilford), 2006-09, Vol.47 (19), p.6874-6879

2006

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FPGA-based convolution neural network for traffic sign recognition

2017 IEEE 12th International Conference on ASIC (ASICON), 2017, p.891-894

2017

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Remote embedded simulation system for SW/HW co-design based on dynamic partial reconfiguration

2017 IEEE 12th International Conference on ASIC (ASICON), 2017, p.402-405

2017

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FPGA bitstream compression and decompression based on LZ77 algorithm and BMC technique

2015 IEEE 11th International Conference on ASIC (ASICON), 2015, p.1-4

2015

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An Efficient Channel-Aware Sparse Binarized Neural Networks Inference Accelerator

IEEE transactions on circuits and systems. II, Express briefs, 2022-03, Vol.69 (3), p.1637-1641

2022

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A power efficient current-mode differential driver for FPGAs

2015 IEEE 11th International Conference on ASIC (ASICON), 2015, p.1-4

2015

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A high throughput FPGA embedded DSP architecture design

2013 IEEE 10th International Conference on ASIC, 2013, p.1-4

2013

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Effect of rubber on properties of nylon-6/unmodified clay/rubber nanocomposites

European polymer journal, 2006-10, Vol.42 (10), p.2515-2522

2006

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Self-Delivery Nanomedicines Reverse Thermal Resistance to Enhance Tumor Mild-Temperature Photothermal Therapy

Molecular pharmaceutics, 2024-03, Vol.21 (3), p.1526-1536

2024

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A Reliable and Efficient Online Solution for Adaptive Voltage and Frequency Scaling on FPGAs

IEEE transactions on very large scale integration (VLSI) systems, 2024-06, Vol.32 (6), p.1058-1071

2024

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Ultrafine full-vulcanized powdered rubbers/PVC compounds with higher toughness and higher heat resistance

Polymer (Guilford), 2005-11, Vol.46 (24), p.10614-10617

2005

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A new model for parametrically evaluating the routability of GRM FPGA

IEICE Electronics Express, 2024-02, Vol.21 (3), p.20230556-20230556, Article 20.20230556

2024

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Biogenic volatile organic compound emissions from Pinus massoniana and Schima superba seedlings: Their responses to foliar and soil application of nitrogen

The Science of the total environment, 2020-02, Vol.705, p.135761, Article 135761

2020

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An Approach of Binary Neural Network Energy-Efficient Implementation

Electronics (Basel), 2021-08, Vol.10 (15), p.1830

2021

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Improved unified interconnect unit for high speed and scalable FPGA

2013 IEEE 10th International Conference on ASIC, 2013, p.1-4

2013

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Weight-based FPGA placement algorithm with wire effect considered

2013 IEEE 10th International Conference on ASIC, 2013, p.1-4

2013

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HBDCA: A Toolchain for High-Accuracy BRAM-Defined CNN Accelerator on FPGA with Flexible Structure

A survey of FPGA design for AI era

FCA-BNN: Flexible and Configurable Accelerator for Binarized Neural Networks on FPGA

A high-performance reconfigurable VLSI architecture for vbsme in H.264

Effect of dispersion of nano-magnesium hydroxide on the flammability of flame retardant ternary composites

Flame retardant synergism of rubber and Mg(OH) 2 in EVA composites

A deep research on the chip verification platform based on network

Application dependent FPGA interconnect test method with small test configuration number using SMT net-grouping constraints

EdgeMedNet: Lightweight and Accurate U-Net for Implementing Efficient Medical Image Segmentation on Edge Devices

Flame retardant nanocomposites of polyamide 6/clay/silicone rubber with high toughness and good flowability

FPGA-based convolution neural network for traffic sign recognition

Remote embedded simulation system for SW/HW co-design based on dynamic partial reconfiguration

FPGA bitstream compression and decompression based on LZ77 algorithm and BMC technique

An Efficient Channel-Aware Sparse Binarized Neural Networks Inference Accelerator

A power efficient current-mode differential driver for FPGAs

A high throughput FPGA embedded DSP architecture design

Effect of rubber on properties of nylon-6/unmodified clay/rubber nanocomposites

Self-Delivery Nanomedicines Reverse Thermal Resistance to Enhance Tumor Mild-Temperature Photothermal Therapy

A Reliable and Efficient Online Solution for Adaptive Voltage and Frequency Scaling on FPGAs

Ultrafine full-vulcanized powdered rubbers/PVC compounds with higher toughness and higher heat resistance

A new model for parametrically evaluating the routability of GRM FPGA

Biogenic volatile organic compound emissions from Pinus massoniana and Schima superba seedlings: Their responses to foliar and soil application of nitrogen

An Approach of Binary Neural Network Energy-Efficient Implementation

Improved unified interconnect unit for high speed and scalable FPGA

Weight-based FPGA placement algorithm with wire effect considered

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