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A 0.004% resolution & SAT<1.8 μson-chip adaptive anti-aging system using cuckoo intelligence-based algorithm in 65 nm CMOS

Integration (Amsterdam), 2021-05, Vol.78, p.135-143

2021

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A 0.0043-mm2 0.085-μW/MHz Relaxation Oscillator Using Charge-Prestored Asymmetric Swings R-RC Network

IEEE transactions on very large scale integration (VLSI) systems, 2023-08, Vol.31 (8), p.1248-1252

2023

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A 0.025% DC Current Mismatch Charge Pump for PLL Applications

2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2021, p.700-703

2021

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A 0.1–4 GHz SDR receiver with reconfigurable 10–100 MHz signal bandwidth in 65 nm CMOS

Analog integrated circuits and signal processing, 2013-12, Vol.77 (3), p.567-582

2013

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A 0.1-6.0-GHz Dual-Path SDR Transmitter Supporting Intraband Carrier Aggregation in 65-nm CMOS

IEEE transactions on very large scale integration (VLSI) systems, 2015-05, Vol.23 (5), p.944-957

2015

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0–1 linear integer programming method for granule knowledge reduction and attribute reduction in concept lattices

Soft computing (Berlin, Germany), 2019-01, Vol.23 (2), p.383-391

2019

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A 0.1-pJ/b and ACF <0.04 Multiple-Valued PUF for Chip Identification Using Bit-Line Sharing Strategy in 65-nm CMOS

IEEE transactions on very large scale integration (VLSI) systems, 2019-05, Vol.27 (5), p.1043-1052

2019

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A 0.116 pJ/bit Latch-Based True Random Number Generator Featuring Static Inverter Selection and Noise Enhancement

IEEE transactions on very large scale integration (VLSI) systems, 2024-03, Vol.32 (3), p.564-572

2024

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A 0.18-ns Response Time Digital LDO Regulator with Adaptive PI Controller in 180-nm CMOS

Electronics (Basel), 2021-07, Vol.10 (14), p.1668

2021

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A 0.18 Um CMOS reconfigurable digital baseband transceiver with 2FSK for RFID

Anti-counterfeiting, Security, and Identification, 2012, p.1-4

2012

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A 0.3-μA Quiescent Current Output Capacitor-Less LDO with Dynamic Slew Rate Enhance Buffer

2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2022, p.1-5

2022

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A 0.3 THz Multi-Beam Extended Interaction Klystron Based on TM10,1,0 Mode Coaxial Coupled Cavity

IEEE access, 2020, Vol.8, p.214383-214391

2020

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A 0.35 μm CMOS mixed controlled crystal oscillator with low phase noise and wide tuning range

Analog integrated circuits and signal processing, 2020-12, Vol.105 (3), p.429-439

2020

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A 0.3GHz-3.3GHz highly linear CMOS LNA for multimode applications

2012 IEEE International Conference on Wireless Information Technology and Systems (ICWITS), 2012, p.1-4

2012

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A 0.4-ps-Jitter −52-dBc-Spur Synthesizable Injection-Locked PLL With Self-Clocked Nonoverlap Update and Slope-Balanced Subsampling BBPD

IEEE solid-state circuits letters, 2019-01, Vol.2 (1), p.5-8

2019

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A 0.4-V Startup, Dead-Zone-Free, Monolithic Four-Mode Synchronous Buck-Boost Converter

IEEE transactions on very large scale integration (VLSI) systems, 2023-07, Vol.31 (7), p.1-10

2023

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A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase locked loop with fine frequency tuning circuits

Science China. Information sciences, 2019-06, Vol.62 (6), p.62405, Article 62405

2019

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A 0.57-GOPS/DSP Object Detection PIM Accelerator on FPGA

2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC), 2021, p.13-14

2021

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A 0.6--2.4 GHz Broadband GaN HEMT Power Amplifier with 79.8% Maximum Drain Efficiency

Industrial IoT Technologies and Applications, 2017, Vol.202, p.214-222

2017

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A 0.72 nW, 1 Sample/s Fully Integrated pH Sensor with 65.8 LSB/pH Sensitivity

2020 IEEE Symposium on VLSI Circuits, 2020, p.1-2

2020

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A 0.78mW Inductor-less 21GHZ CML frequency divider in 65nm CMOS

2019 IEEE 3rd Information Technology, Networking, Electronic and Automation Control Conference (ITNEC), 2019, p.1395-1399

2019

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A 0.8V Chopper Amplifier with 600mVpp Tolerance to Power-Line Interference for Neural Signal Acquisition

2019 IEEE Biomedical Circuits and Systems Conference (BioCAS), 2019, p.1-4

2019

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A 0.9-2.25-GHz Sub-0.2-mW/GHz Compact Low-Voltage Low-Power Hybrid Digital PLL With Loop Bandwidth-Tracking Technique

IEEE transactions on very large scale integration (VLSI) systems, 2018-05, Vol.26 (5), p.933-944

2018

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A 0.9 V low-power reconfigurable successive approximation ADC for integrated sensors

2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS), 2013, p.1-4

2013

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L 0 -Regularized Learning for High-Dimensional Additive Hazards Regression

INFORMS journal on computing, 2022-09, Vol.34 (5), p.2762-2775

2022

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A 0.004% resolution & SAT<1.8 μson-chip adaptive anti-aging system using cuckoo intelligence-based algorithm in 65 nm CMOS

A 0.0043-mm2 0.085-μW/MHz Relaxation Oscillator Using Charge-Prestored Asymmetric Swings R-RC Network

A 0.025% DC Current Mismatch Charge Pump for PLL Applications

A 0.1–4 GHz SDR receiver with reconfigurable 10–100 MHz signal bandwidth in 65 nm CMOS

A 0.1-6.0-GHz Dual-Path SDR Transmitter Supporting Intraband Carrier Aggregation in 65-nm CMOS

0–1 linear integer programming method for granule knowledge reduction and attribute reduction in concept lattices

A 0.1-pJ/b and ACF <0.04 Multiple-Valued PUF for Chip Identification Using Bit-Line Sharing Strategy in 65-nm CMOS

A 0.116 pJ/bit Latch-Based True Random Number Generator Featuring Static Inverter Selection and Noise Enhancement

A 0.18-ns Response Time Digital LDO Regulator with Adaptive PI Controller in 180-nm CMOS

A 0.18 Um CMOS reconfigurable digital baseband transceiver with 2FSK for RFID

A 0.3-μA Quiescent Current Output Capacitor-Less LDO with Dynamic Slew Rate Enhance Buffer

A 0.3 THz Multi-Beam Extended Interaction Klystron Based on TM10,1,0 Mode Coaxial Coupled Cavity

A 0.35 μm CMOS mixed controlled crystal oscillator with low phase noise and wide tuning range

A 0.3GHz-3.3GHz highly linear CMOS LNA for multimode applications

A 0.4-ps-Jitter −52-dBc-Spur Synthesizable Injection-Locked PLL With Self-Clocked Nonoverlap Update and Slope-Balanced Subsampling BBPD

A 0.4-V Startup, Dead-Zone-Free, Monolithic Four-Mode Synchronous Buck-Boost Converter

A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase locked loop with fine frequency tuning circuits

A 0.57-GOPS/DSP Object Detection PIM Accelerator on FPGA

A 0.6--2.4 GHz Broadband GaN HEMT Power Amplifier with 79.8% Maximum Drain Efficiency

A 0.72 nW, 1 Sample/s Fully Integrated pH Sensor with 65.8 LSB/pH Sensitivity

A 0.78mW Inductor-less 21GHZ CML frequency divider in 65nm CMOS

A 0.8V Chopper Amplifier with 600mVpp Tolerance to Power-Line Interference for Neural Signal Acquisition

A 0.9-2.25-GHz Sub-0.2-mW/GHz Compact Low-Voltage Low-Power Hybrid Digital PLL With Loop Bandwidth-Tracking Technique

A 0.9 V low-power reconfigurable successive approximation ADC for integrated sensors

L 0 -Regularized Learning for High-Dimensional Additive Hazards Regression

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