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All-Solution-Processed Metallization of High Aspect Ratio Through Glass Vias (HAR-TGVs) with a High Adhesion Promoting Layer (APL)
2023 18th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2023, p.251-254
2023
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Low-cost 3DIC process technologies for wide-I/O memory cube
2015 International Symposium on VLSI Technology, Systems and Applications, 2015, p.1-2
2015
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Process integration of 3D Si interposer with double-sided active chip attachments
2013 IEEE 63rd Electronic Components and Technology Conference, 2013, p.86-93
2013
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Fine-pitch backside via-last TSV process with optimization on temporary glue and bonding conditions
2013 IEEE 63rd Electronic Components and Technology Conference, 2013, p.1811-1814
2013
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A novel fabrication process and measurement results of a 28GHz glass antenna with single TGV for 5G communication applications
2019 14th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2019, p.112-115
2019
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Challenges of Cu CMP of TSVs and RDLs fabricated from the backside of a thin wafer
2013 IEEE International 3D Systems Integration Conference (3DIC), 2013, p.1-5
2013
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Technologies and challenges of fine-pitch backside via-last 3DIC TSV process integration and its electrical characteristics and system applications
Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2014, p.1-2
2014
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Study of TSV filling performance with wide-range pattern densities by using a novel plating chamber with surface paddle agitation
2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2013, p.1-2
2013
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Backside-TSV process development and integration for 2∼3um small size TSV
2016 11th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2016, p.273-276
2016
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Implementation of memory stacking on logic controller by using 3DIC 300mm backside TSV process integration
2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2016, p.1-2
2016
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An innovative bumpless stacking with through silicon via for 3D Wafer-on-Wafer (WOW) integration
2014 IEEE 64th Electronic Components and Technology Conference (ECTC), 2014, p.1853-1856
2014
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