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A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices

2023 IEEE International Solid- State Circuits Conference (ISSCC), 2023, p.126-128

2023

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34.2 A 16nm 96Kb Integer/Floating-Point Dual-Mode-Gain-Cell-Computing-in-Memory Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge Devices

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.568-570

2024

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A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices

2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, Vol.65, p.1-3

2022

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RRAM-based Spiking Nonvolatile Computing-In-Memory Processing Engine with Precision-Configurable In Situ Nonlinear Activation

2019 Symposium on VLSI Technology, 2019, p.T86-T87

2019

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A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training

2020 57th ACM/IEEE Design Automation Conference (DAC), 2020, p.1-6

2020

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MSig-BFT: A Witness-Based Consensus Algorithm for Private Blockchains

2018 IEEE 24th International Conference on Parallel and Distributed Systems (ICPADS), 2018, p.992-997

2018

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16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips

2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, Vol.64, p.250-252

2021

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Circuit Design Challenges in Computing-in-Memory for AI Edge Devices

2019 IEEE 13th International Conference on ASIC (ASICON), 2019, p.1-4

2019

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A 16Mb dual-mode ReRAM macro with sub-14ns computing-in-memory and memory functions enabled by self-write termination scheme

2017 IEEE International Electron Devices Meeting (IEDM), 2017, p.28.2.1-28.2.4

2017

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A study on modular design representation

2007 IEEE International Conference on Industrial Engineering and Engineering Management, 2007, p.1327-1331

2007

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15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips

2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020, p.246-248

2020

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A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors

2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2019, p.217-218

2019

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15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips

2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020, p.240-242

2020

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A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration

2021 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2021, p.1-3

2021

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BEOL-Compatible Multiple Metal-Ferroelectric-Metal (m-MFM) FETs Designed for Low Voltage (2.5 V), High Density, and Excellent Reliability

2020 IEEE International Electron Devices Meeting (IEDM), 2020, p.4.6.1-4.6.4

2020

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Empowering Local Differential Privacy: A 5718 TOPS/W Analog PUF-Based In-Memory Encryption Macro for Dynamic Edge Security

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2

2024

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15.2 A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating

2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, Vol.64, p.238-240

2021

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Improving Edge Dead Domain and Endurance in Scaled HfZrOx FeRAM

2021 IEEE International Electron Devices Meeting (IEDM), 2021, p.6.4.1-6.4.4

2021

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Highly Reliable, Scalable, and High-Yield HfZrOx FRAM by Barrier Layer Engineering and Post-Metal Annealing

2022 International Electron Devices Meeting (IEDM), 2022, p.32.1.1-32.1.4

2022

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A two-way SRAM array based accelerator for deep neural network on-chip training

Proceedings of the 57th ACM/EDAC/IEEE Design Automation Conference, 2020, p.1-6

2020

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Research on Cardiac Function Monitoring Technique Based on Ballistocardiogram

Su, Wei Jian

2010

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Notice of Retraction: Investigation of Treatment of Domestic Sewage by PAC-SBR Process

2011 5th International Conference on Bioinformatics and Biomedical Engineering, 2011, p.1-4

2011

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iMirror: An Intelligent Gait Recognition Mirror for Rehabilitation of Patients with Parkinson's Disease

2023 IEEE International Conference on Consumer Electronics (ICCE), 2023, p.1-3

2023

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Association Analysis of Gene Expression and Brain Image Identifies Gene Signatures in Major Depression Disorder

Cognitive Computation and Systems, p.148-159

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Detection of SDN Flow Rule Conflicts Based on Knowledge Graph

Emerging Networking Architecture and Technologies, p.93-104

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A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices

34.2 A 16nm 96Kb Integer/Floating-Point Dual-Mode-Gain-Cell-Computing-in-Memory Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge Devices

A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices

RRAM-based Spiking Nonvolatile Computing-In-Memory Processing Engine with Precision-Configurable In Situ Nonlinear Activation

A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training

MSig-BFT: A Witness-Based Consensus Algorithm for Private Blockchains

16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips

Circuit Design Challenges in Computing-in-Memory for AI Edge Devices

A 16Mb dual-mode ReRAM macro with sub-14ns computing-in-memory and memory functions enabled by self-write termination scheme

A study on modular design representation

15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips

A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors

15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips

A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration

BEOL-Compatible Multiple Metal-Ferroelectric-Metal (m-MFM) FETs Designed for Low Voltage (2.5 V), High Density, and Excellent Reliability

Empowering Local Differential Privacy: A 5718 TOPS/W Analog PUF-Based In-Memory Encryption Macro for Dynamic Edge Security

15.2 A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating

Improving Edge Dead Domain and Endurance in Scaled HfZrOx FeRAM

Highly Reliable, Scalable, and High-Yield HfZrOx FRAM by Barrier Layer Engineering and Post-Metal Annealing

A two-way SRAM array based accelerator for deep neural network on-chip training

Research on Cardiac Function Monitoring Technique Based on Ballistocardiogram

Notice of Retraction: Investigation of Treatment of Domestic Sewage by PAC-SBR Process

iMirror: An Intelligent Gait Recognition Mirror for Rehabilitation of Patients with Parkinson's Disease

Association Analysis of Gene Expression and Brain Image Identifies Gene Signatures in Major Depression Disorder

Detection of SDN Flow Rule Conflicts Based on Knowledge Graph

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