UB Paderborn / Katalog / Suche / in CDI

Visual statistics: seeing data with dynamic interactive graphics

1, 2011

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Digital Twin Design and Evaluation for Dynamically Optimised Distribution Strategy in Food Supply Chains: An Exploratory Case Study

Flexible Automation and Intelligent Manufacturing: Establishing Bridges for More Sustainable Manufacturing Systems, p.687-695

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Dynamically Controlled Resource Allocation in SMT Processors

37th International Symposium on Microarchitecture (MICRO-37'04), 2004, p.171-182

2004

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Regulatory Mechanisms of Muscle Mass: The Critical Role of Resistance Training in Children and Adolescent

Advances in experimental medicine and biology, 2023, Vol.1410, p.21-34

2023

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Class AB two stage and folded cascode OpAmps based on a squaring circuit

2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015, p.253-256

2015

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Designing OS for HPC Applications: Scheduling

2010 IEEE International Conference on Cluster Computing, 2010, p.78-87

2010

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Out-of-order commit processors

10th International Symposium on High Performance Computer Architecture (HPCA'04), 2004, p.48-59

2004

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Improving Cache Management Policies Using Dynamic Reuse Distances

2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012, p.389-400

2012

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Multiple-banked register file architectures

International Symposium on Computer Architecture: Proceedings of the 27th annual international symposium on Computer architecture : Vancouver, British Columbia, Canada, 2000, p.316-325

2000

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An ultra low-power low-voltage class AB CMOS fully differential OpAmp

2012 IEEE International Symposium on Circuits and Systems (ISCAS), 2012, p.1967-1970

2012

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High Performance Computing - HiPC 2000: 7th International Conference Bangalore, India, December 17-20, 2000 Proceedings

1, 2000

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Delaying physical register allocation through virtual-physical registers

MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture, 1999, p.186-192

1999

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Power efficient topologies for wireless sensor networks

International Conference on Parallel Processing, 2001, 2001, p.156-163

2001

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Exploiting a new level of DLP in multimedia applications

MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture, 1999, p.72-79

1999

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Two-level hierarchical register file organization for VLIW processors

Proceedings 33rd Annual IEEE/ACM International Symposium on Microarchitecture. MICRO-33 2000, 2000, p.137-146

2000

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Task Superscalar: An Out-of-Order Task Pipeline

2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010, p.89-100

2010

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On calculating power-aware connected dominating sets for efficient routing in ad hoc wireless networks

International Conference on Parallel Processing, 2001, 2001, p.346-354

2001

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A CMOS 1.2-V 1.7-mW lock-in amplifier for sensing applications up to 0.7-MHz

IEEE SENSORS 2014 Proceedings, 2014, p.78-81

2014

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On-the-Fly Adaptive Routing in High-Radix Hierarchical Networks

2012 41st International Conference on Parallel Processing, 2012, p.279-288

2012

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EazyHTM: eager-lazy hardware transactional memory

2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2009, p.145-155

2009

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Hardware schemes for early register release

Proceedings International Conference on Parallel Processing, 2002, p.5-13

2002

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Fetching instruction streams

35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings, 2002, p.371-382

2002

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On the efficiency of reductions in mu -SIMD media extensions

Proceedings of the Conference on Parallel Architectures and Compilation Techniques, 2001

2001

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Vector Extensions for Decision Support DBMS Acceleration

2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012, p.166-176

2012

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Out-of-order vector architectures

Proceedings of 30th Annual International Symposium on Microarchitecture, 1997, p.160-170

1997

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Visual statistics: seeing data with dynamic interactive graphics

Digital Twin Design and Evaluation for Dynamically Optimised Distribution Strategy in Food Supply Chains: An Exploratory Case Study

Dynamically Controlled Resource Allocation in SMT Processors

Regulatory Mechanisms of Muscle Mass: The Critical Role of Resistance Training in Children and Adolescent

Class AB two stage and folded cascode OpAmps based on a squaring circuit

Designing OS for HPC Applications: Scheduling

Out-of-order commit processors

Improving Cache Management Policies Using Dynamic Reuse Distances

Multiple-banked register file architectures

An ultra low-power low-voltage class AB CMOS fully differential OpAmp

High Performance Computing - HiPC 2000: 7th International Conference Bangalore, India, December 17-20, 2000 Proceedings

Delaying physical register allocation through virtual-physical registers

Power efficient topologies for wireless sensor networks

Exploiting a new level of DLP in multimedia applications

Two-level hierarchical register file organization for VLIW processors

Task Superscalar: An Out-of-Order Task Pipeline

On calculating power-aware connected dominating sets for efficient routing in ad hoc wireless networks

A CMOS 1.2-V 1.7-mW lock-in amplifier for sensing applications up to 0.7-MHz

On-the-Fly Adaptive Routing in High-Radix Hierarchical Networks

EazyHTM: eager-lazy hardware transactional memory

Hardware schemes for early register release

Fetching instruction streams

On the efficiency of reductions in mu -SIMD media extensions

Vector Extensions for Decision Support DBMS Acceleration

Out-of-order vector architectures

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