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A landmark based registration technique for minimally invasive spinal surgery

2013 IEEE International Symposium on Consumer Electronics (ISCE), 2013, p.235-236

2013

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An brain-computer interface for video content analysis system for perceive emotions by using EEG

2016 IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW), 2016, p.1-2

2016

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A computed stereoscopic method for laparoscopic surgery by using feature tracking

2015 IEEE International Conference on Consumer Electronics - Taiwan, 2015, p.9-10

2015

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Studies of C/EBP transcription factors in myelomonocytic cell lineages

Hu, Hsien-Ming

1998

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A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist

International Symposium on Low Power Electronics and Design (ISLPED), 2013, p.51-56

2013

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A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist

2013 IEEE International Symposium on Circuits and Systems (ISCAS), 2013, p.1468-1471

2013

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Comparing the effects of robots and IoT objects on STEM learning outcomes and computational thinking skills between programming-experienced learners and programming-novice learners

2020 IEEE 20th International Conference on Advanced Learning Technologies (ICALT), 2020, p.87-89

2020

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A reconfigurable MAC architecture implemented with mixed-Vt standard cell library

2008 IEEE International Symposium on Circuits and Systems, 2008, p.3426-3429

2008

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A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists

2014 27th IEEE International System-on-Chip Conference (SOCC), 2014, p.455-462

2014

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A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control

2013 IEEE International SOC Conference, 2013, p.110-115

2013

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A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist

Proceedings of the 2013 International Symposium on Low Power Electronics and Design, 2013, p.51-56

2013

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The effects of constructing robot-based storytelling system on college students' computational thinking skill and technology comprehension

2022 24th International Conference on Advanced Communication Technology (ICACT), 2022, p.496-500

2022

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10.3 heterogeneous multi-processing quad-core CPU and dual-GPU design for optimal performance, power, and thermal tradeoffs in a 28nm mobile application processor

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014, p.180-181

2014

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A landmark based registration technique for minimally invasive spinal surgery

An brain-computer interface for video content analysis system for perceive emotions by using EEG

A computed stereoscopic method for laparoscopic surgery by using feature tracking

Studies of C/EBP transcription factors in myelomonocytic cell lineages

A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist

A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist

Comparing the effects of robots and IoT objects on STEM learning outcomes and computational thinking skills between programming-experienced learners and programming-novice learners

A reconfigurable MAC architecture implemented with mixed-Vt standard cell library

A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists

A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control

A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist

The effects of constructing robot-based storytelling system on college students' computational thinking skill and technology comprehension

10.3 heterogeneous multi-processing quad-core CPU and dual-GPU design for optimal performance, power, and thermal tradeoffs in a 28nm mobile application processor

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