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Dual-addressing memory architecture for two-dimensional memory access patterns

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, p.71-76

2013

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A novel cache-utilization based dynamic voltage frequency scaling (DVFS) mechanism for reliability enhancements

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, p.79-84

2016

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Performance-driven dual-rail insertion for chip-level pre-fabricated design

Proceedings of the Conference on Design, Automation and Test in Europe, 2009, p.308-311

2009

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Wire Sizing Alternative - An Uniform Dual-rail Routing Architecture

2008 Design, Automation and Test in Europe, 2008, p.796-799

2008

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Design and Evaluation of a Bi-directional Data Acquisition and Control System for Small-scale Solar Power Plants

2019 4th International Conference on Intelligent Green Building and Smart Grid (IGBSG), 2019, p.339-344

2019

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Non-linguistic Features for Cyberbullying Detection on a Social Media Platform Using Machine Learning

Cyberspace Safety and Security, p.391-406

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Guiding Template Design for Lamellar DSA with Multiple Patterning and Self-Aligned Via Process

2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020, p.1-6

2020

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Crosstalk-aware Domino Logic Synthesis

Proceedings of the Design Automation & Test in Europe Conference, 2006, Vol.1, p.1-6

2006

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The Relationship between Managerial Support and Job Training Satisfaction with the Mediation Effect of Learning Motivation

Liu, Yi-Yu

2020

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The Advances of Stemming Algorithms in Text Analysis from 2013 to 2018

Liu, Yi-Yu Bruce

2019

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Binary decision diagram with minimum expected path length

Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, 2001, p.708-712

2001

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Crosstalk minimization in logic synthesis for PLA

Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004, Vol.2, p.790-795 Vol.2

2004

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An efficient hybrid LUT/SOP reconfigurable architecture

Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, 2010, p.173-176

2010

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Dangling-wire avoidance routing for crossbar switch structured ASIC design style

Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, 2010, p.177-180

2010

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Identifying Prostate Cancer-Related Networks from Microarray Data Based on Genotype-Phenotype Networks Using Markov Blanket Search

2010 IEEE International Conference on BioInformatics and BioEngineering, 2010, p.302-303

2010

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Buffer design and optimization for lut-based structured ASIC design styles

Proceedings of the 19th ACM Great Lakes symposium on VLSI, 2009, p.377-380

2009

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Research on Product Platform Innovation and Evolution Based on Lifecycle

Key engineering materials, 2010, Vol.431-432, p.285-288

2010

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Performance-driven dual-rail insertion for chip-level pre-fabricated design

2009 Design, Automation & Test in Europe Conference & Exhibition, 2009, p.308-311

2009

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Guiding template design for lamellar DSA with multiple patterning and self-aligned via process

Proceedings of the 39th International Conference on Computer-Aided Design, 2020, p.1-6

2020

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Study on environmental emergency capability assessment based on fuzzy comprehensive evaluation-case of dalian

Liu, Yi Yu

2010

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Study on dual cameras vision measurement system using a lightpen

Liu, Yi Yu

2010

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Research on knowledge-driven product platform innvoation of complicated equipments

Liu, Yu Yi

2010

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Construction of minimal delay Steiner tree using two-pole delay model

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455), 2001, p.126-131

2001

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Dual-addressing memory architecture for two-dimensional memory access patterns

Proceedings of the Conference on Design, Automation and Test in Europe, 2013, p.71-76

2013

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Wire sizing alternative: an uniform dual-rail routing architecture

Proceedings of the conference on Design, automation and test in Europe, 2008, p.796-799

2008

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Dual-addressing memory architecture for two-dimensional memory access patterns

A novel cache-utilization based dynamic voltage frequency scaling (DVFS) mechanism for reliability enhancements

Performance-driven dual-rail insertion for chip-level pre-fabricated design

Wire Sizing Alternative - An Uniform Dual-rail Routing Architecture

Design and Evaluation of a Bi-directional Data Acquisition and Control System for Small-scale Solar Power Plants

Non-linguistic Features for Cyberbullying Detection on a Social Media Platform Using Machine Learning

Guiding Template Design for Lamellar DSA with Multiple Patterning and Self-Aligned Via Process

Crosstalk-aware Domino Logic Synthesis

The Relationship between Managerial Support and Job Training Satisfaction with the Mediation Effect of Learning Motivation

The Advances of Stemming Algorithms in Text Analysis from 2013 to 2018

Binary decision diagram with minimum expected path length

Crosstalk minimization in logic synthesis for PLA

An efficient hybrid LUT/SOP reconfigurable architecture

Dangling-wire avoidance routing for crossbar switch structured ASIC design style

Identifying Prostate Cancer-Related Networks from Microarray Data Based on Genotype-Phenotype Networks Using Markov Blanket Search

Buffer design and optimization for lut-based structured ASIC design styles

Research on Product Platform Innovation and Evolution Based on Lifecycle

Performance-driven dual-rail insertion for chip-level pre-fabricated design

Guiding template design for lamellar DSA with multiple patterning and self-aligned via process

Study on environmental emergency capability assessment based on fuzzy comprehensive evaluation-case of dalian

Study on dual cameras vision measurement system using a lightpen

Research on knowledge-driven product platform innvoation of complicated equipments

Construction of minimal delay Steiner tree using two-pole delay model

Dual-addressing memory architecture for two-dimensional memory access patterns

Wire sizing alternative: an uniform dual-rail routing architecture

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