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Modeling of Negative Bias Temperature Instability (NBTI) for Gate-All-Around (GAA) Stacked Nanosheet Technology

2024 IEEE International Reliability Physics Symposium (IRPS), 2024, p.7B.5-1-7B.5-6

2024

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Understanding the impact of polysilicon percolative conduction on 3D NAND variability

2023 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2023, p.97-100

2023

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Challenges in Design and Modeling of Cold CMOS HPC Technology

2021 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2021, p.107-110

2021

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Simulation-based DRAM Design Technology Co-Optimization: Why Random Dopant Fluctuations Matter

2021 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2021, p.188-191

2021

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High-sigma analysis of DRAM write and retention performance: a TCAD-to-SPICE approach

2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2020, p.35-38

2020

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Modeling and Optimization of Advanced 3D NAND Memory

2020 Device Research Conference (DRC), 2020, p.1-2

2020

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Power-performance-area engineering of 5nm nanowire library cells

2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2015, p.433-436

2015

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Study of the impact of charge-neutrality level (CNL) of grain boundary interface trap on device variability and P/E cycling endurance of 3D NAND flash memory

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014, p.1-2

2014

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Logic Block Level Design-Technology Co-Optimization is the New Moore's Law (Invited)

2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 2020, p.1-4

2020

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Modeling and Simulation for DRAM and Flash Memory Technology Exploration and Development

2024 IEEE International Memory Workshop (IMW), 2024, p.1-4

2024

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Charge storage efficiency (CSE) effect in modeling the incremental step pulse programming (ISPP) in charge-trapping 3D NAND flash devices

2015 IEEE International Electron Devices Meeting (IEDM), 2015, p.5.5.1-5.5.4

2015

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3DIC System-Technology Co-Optimization with a Focus on the Interplay of Thermal, Power, Timing, and Stress Effects

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2

2024

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Impact of Fabrication Process, Layout Variation and Packaging Process on Cu/Low-k Interconnect Reliability

MRS proceedings, 2007, Vol.990, Article 0990-B10-02

2007

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A Multiscale Statistical Evaluation of DRAM Variable Retention Time

2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 2021, p.1-3

2021

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Transmission spectrum of coaxial localized-defected Bragg structures with uniform and inhomogeneous ripples

Asia-Pacific Microwave Conference 2011, 2011, p.813-816

2011

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Effect of defect location and corrugation phase on transmission in a defected coaxial Bragg structure with two corrugated surfaces

2012 Asia Pacific Microwave Conference Proceedings, 2012, p.556-558

2012

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Stress-Aware Design Methodology

7th International Symposium on Quality Electronic Design (ISQED'06), 2006, p.807-812

2006

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Application of Inductive Learning in Human Brain CT Image Recognition

2007 International Conference on Machine Learning and Cybernetics, 2007, Vol.3, p.1667-1671

2007

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Multiwave interaction analysis of a coaxial Bragg structure with a localized defect introduced in sinusoidal corrugations

2009 Asia Pacific Microwave Conference, 2009, p.457-460

2009

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Modeling and optimization of group IV and III-V FinFETs and nano-wires

2014 IEEE International Electron Devices Meeting, 2014, p.7.4.1-7.4.4

2014

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Layout proximity effects and device extraction in circuit designs

2008 9th International Conference on Solid-State and Integrated-Circuit Technology, 2008, p.2228-2231

Xi-Wei Lin

2008

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Memory Window and Variability Modeling of Multi- Domain Al:HfO2Ferroelectric NAND Memory

2024 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2024, p.01-04

2024

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A Multiscale Simulation Approach for Program Noise and Cross-temperature Effects in 3D NANDs

2024 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2024, p.1-4

2024

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Design for manufacturing with increasing variability

2005 6th International Conference on ASIC, 2005, Vol.1, p.1175-1179

Xi-Wei Lin

2005

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Process Induced Layout Variability for Sub 90nm Technologies

2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings, 2006, p.1849-1852

2006

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Modeling of Negative Bias Temperature Instability (NBTI) for Gate-All-Around (GAA) Stacked Nanosheet Technology

Understanding the impact of polysilicon percolative conduction on 3D NAND variability

Challenges in Design and Modeling of Cold CMOS HPC Technology

Simulation-based DRAM Design Technology Co-Optimization: Why Random Dopant Fluctuations Matter

High-sigma analysis of DRAM write and retention performance: a TCAD-to-SPICE approach

Modeling and Optimization of Advanced 3D NAND Memory

Power-performance-area engineering of 5nm nanowire library cells

Study of the impact of charge-neutrality level (CNL) of grain boundary interface trap on device variability and P/E cycling endurance of 3D NAND flash memory

Logic Block Level Design-Technology Co-Optimization is the New Moore's Law (Invited)

Modeling and Simulation for DRAM and Flash Memory Technology Exploration and Development

Charge storage efficiency (CSE) effect in modeling the incremental step pulse programming (ISPP) in charge-trapping 3D NAND flash devices

3DIC System-Technology Co-Optimization with a Focus on the Interplay of Thermal, Power, Timing, and Stress Effects

Impact of Fabrication Process, Layout Variation and Packaging Process on Cu/Low-k Interconnect Reliability

A Multiscale Statistical Evaluation of DRAM Variable Retention Time

Transmission spectrum of coaxial localized-defected Bragg structures with uniform and inhomogeneous ripples

Effect of defect location and corrugation phase on transmission in a defected coaxial Bragg structure with two corrugated surfaces

Stress-Aware Design Methodology

Application of Inductive Learning in Human Brain CT Image Recognition

Multiwave interaction analysis of a coaxial Bragg structure with a localized defect introduced in sinusoidal corrugations

Modeling and optimization of group IV and III-V FinFETs and nano-wires

Layout proximity effects and device extraction in circuit designs

Memory Window and Variability Modeling of Multi- Domain Al:HfO2Ferroelectric NAND Memory

A Multiscale Simulation Approach for Program Noise and Cross-temperature Effects in 3D NANDs

Design for manufacturing with increasing variability

Process Induced Layout Variability for Sub 90nm Technologies

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