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Cloud platforms and embedded computing: the operating systems of the future

2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), 2013, p.1-6

2013

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Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory

2009 Symposium on VLSI Technology, 2009, p.192-193

2009

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Register Array Structure for Effective Edge Filtering Operation of Deblocking Filter

Embedded and Ubiquitous Computing, 2006, p.805-813

2006

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A Deep Multi-Object Tracking Technique in Swimming Video Scenes

2023 IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia), 2023, p.1-4

2023

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Leak detection for cloud-based IoT devices

2017 IEEE 7th International Conference on Consumer Electronics - Berlin (ICCE-Berlin), 2017, p.90-91

2017

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Twin silicon nanowire FET (TSNWFET) On SOI with 8 nm silicon nanowires and 25 nm surrounding TiN gate

2008 IEEE International SOI Conference, 2008, p.117-118

2008

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Development of 38nm Bit-Lines using Copper Damascene Process for 64-Giga bits NAND Flash

2008 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, 2008, p.49-51

2008

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Sub-10 nm gate-all-around CMOS nanowire transistors on bulk Si substrate

2009 Symposium on VLSI Technology, 2009, p.94-95

2009

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Implementation of an image signal processor for reconfigurable processors

2014 IEEE International Conference on Consumer Electronics (ICCE), 2014, p.141-142

2014

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Evaluation of Ultra Thin Body Si-On-ONO (UTB SOONO) transistors using ultra thin spacer technology

2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial, 2008, p.5-8

2008

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Highly scalable NAND flash memory with robust immunity to program disturbance using symmetric inversion-type source and drain structure

2008 Symposium on VLSI Technology, 2008, p.118-119

2008

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Investigation of nanowire size dependency on TSNWFET

2007 IEEE International Electron Devices Meeting, 2007, p.891-894

2007

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A Light-weight stereo matching network for an embedded vision system

2020 International Conference on Information and Communication Technology Convergence (ICTC), 2020, p.1234-1237

2020

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Stereo Matching Validation using Spherical Image Mapping

2018 International Conference on Information and Communication Technology Convergence (ICTC), 2018, p.1127-1130

2018

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Isotropic Blur Identification for Fully Digital Auto-focusing

Image Analysis and Recognition, 2005, p.125-132

1ère éd, 2005

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Selective just-in-time compilation for client-side mobile javascript engine

2011 Proceedings of the 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES), 2011, p.5-14

2011

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Future memory technologies

2008 9th International Conference on Solid-State and Integrated-Circuit Technology, 2008, p.1-4

Won-Seong Lee

2008

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Effect of Pre-stressed Thermal Ageing and Electric Field during Measurement on Space Charge Distribution of HVDC Insulating Materials

2022 9th International Conference on Condition Monitoring and Diagnosis (CMD), 2022, p.786-789

2022

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Characteristics of sub 5nm tri-gate nanowire MOSFETs with single and poly Si channels in SOI structure

2009 Symposium on VLSI Technology, 2009, p.142-143

2009

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Edge-based Error Concealment for Line Compression Methods

2018 International Conference on Information and Communication Technology Convergence (ICTC), 2018, p.463-465

2018

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Code size and performance optimization for mobile JavaScript just-in-time compiler

Proceedings of the 2010 Workshop on Interaction between Compilers and Computer Architecture, 2010, p.1-7

2010

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A novel thin BOX SOI technology using bulk Si wafer for system-on-chip (SoC) application

2009 Symposium on VLSI Technology, 2009, p.96-97

2009

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Experimental Investigation on Superior PMOS Performance of Uniaxial Strained ≪110≫ Silicon Nanowire Channel By Embedded SiGe Source/Drain

2007 IEEE International Electron Devices Meeting, 2007, p.899-902

2007

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Quarter-pel Interpolation Architecture in H.264/AVC Decoder

The 2007 International Conference on Intelligent Pervasive Computing (IPC 2007), 2007, p.224-227

2007

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Charge trapping induced DRAM data retention time degradation under wafer-level burn-in stress

2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320), 2002, p.287-291

2002

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Cloud platforms and embedded computing: the operating systems of the future

Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory

Register Array Structure for Effective Edge Filtering Operation of Deblocking Filter

A Deep Multi-Object Tracking Technique in Swimming Video Scenes

Leak detection for cloud-based IoT devices

Twin silicon nanowire FET (TSNWFET) On SOI with 8 nm silicon nanowires and 25 nm surrounding TiN gate

Development of 38nm Bit-Lines using Copper Damascene Process for 64-Giga bits NAND Flash

Sub-10 nm gate-all-around CMOS nanowire transistors on bulk Si substrate

Implementation of an image signal processor for reconfigurable processors

Evaluation of Ultra Thin Body Si-On-ONO (UTB SOONO) transistors using ultra thin spacer technology

Highly scalable NAND flash memory with robust immunity to program disturbance using symmetric inversion-type source and drain structure

Investigation of nanowire size dependency on TSNWFET

A Light-weight stereo matching network for an embedded vision system

Stereo Matching Validation using Spherical Image Mapping

Isotropic Blur Identification for Fully Digital Auto-focusing

Selective just-in-time compilation for client-side mobile javascript engine

Future memory technologies

Effect of Pre-stressed Thermal Ageing and Electric Field during Measurement on Space Charge Distribution of HVDC Insulating Materials

Characteristics of sub 5nm tri-gate nanowire MOSFETs with single and poly Si channels in SOI structure

Edge-based Error Concealment for Line Compression Methods

Code size and performance optimization for mobile JavaScript just-in-time compiler

A novel thin BOX SOI technology using bulk Si wafer for system-on-chip (SoC) application

Experimental Investigation on Superior PMOS Performance of Uniaxial Strained ≪110≫ Silicon Nanowire Channel By Embedded SiGe Source/Drain

Quarter-pel Interpolation Architecture in H.264/AVC Decoder

Charge trapping induced DRAM data retention time degradation under wafer-level burn-in stress

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