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Hardware design of Euclidean Projection modules for ADMM LDPC decoding

2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2018, p.73-76

2018

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Design of a reconfigurable digital decimation filter for flexible GNSS receivers

2016 5th International Conference on Multimedia Computing and Systems (ICMCS), 2016, p.230-235

2016

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A survey on decoding schedules of LDPC convolutional codes and associated hardware architectures

2017 IEEE Symposium on Computers and Communications (ISCC), 2017, p.898-905

2017

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Comparison of different schedulings for the ADMM based LDPC decoding

2016 9th International Symposium on Turbo Codes and Iterative Information Processing (ISTC), 2016, p.51-55

2016

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Implementation aspects of a pipeline ADMM-based LP decoding of LDPC convolutional codes

2018 IEEE Wireless Communications and Networking Conference (WCNC), 2018, p.1-6

2018

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ADMM hardware decoder for regular LDPC codes using a NISC-based architecture

2018 IEEE Wireless Communications and Networking Conference (WCNC), 2018, p.1-6

2018

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Multicore implementation of LDPC decoders based on ADMM algorithm

2016 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2016, p.971-975

2016

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A Comparative Evaluation of Well-known Feature Extractors for Multi-view Vehicle Tracking in VSNs

2022 IEEE Ninth International Conference on Communications and Networking (ComNet), 2022, p.1-6

2022

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Deep Multi-modal Object Detection for Autonomous Driving

2021 18th International Multi-Conference on Systems, Signals & Devices (SSD), 2021, p.7-11

2021

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Feature-based Vehicle Tracking at Roundabouts in Visual Sensor Networks

2020 17th International Multi-Conference on Systems, Signals & Devices (SSD), 2020, p.167-172

2020

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Design and Implementation of a Reconfigurable Decimation and Channel Selection Filter for GSM and UMTS Radio Standards

2009 IEEE Wireless Communications and Networking Conference, 2009, p.1-6

2009

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Low complexity ADMM-LP based decoding strategy for LDPC convolutional codes

2017 25th International Conference on Software, Telecommunications and Computer Networks (SoftCOM), 2017, p.1-5

2017

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Reduced complexity ADMM-based schedules for LP decoding of LDPC convolutional codes

2017 IEEE International Workshop on Signal Processing Systems (SiPS), 2017, p.1-6

2017

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Hardware complexity reduction of LDPC-CC decoders based on message-passing approaches

2016 17th International Conference on Sciences and Techniques of Automatic Control and Computer Engineering (STA), 2016, p.679-684

2016

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An LP-based algorithm for decoding terminated LDPC convolutional codes

2017 International Conference on Internet of Things, Embedded Systems and Communications (IINTEC), 2017, p.95-100

2017

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A reconfigurable Digital Down Converter architecture for multistandard GNSS receiver

2014 14th International Symposium on Communications and Information Technologies (ISCIT), 2014, p.404-408

2014

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Analysis of ADMM-LP algorithm for LDPC decoding, a first step to hardware implementation

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2015, p.356-359

2015

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Experiments on designing low power decimation filter for multistandard receiver on heterogeneous targets

2009 17th European Signal Processing Conference, 2009, p.1284-1288

2009

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Power consumption estimation models for FIR decimation filters in multi-standard receivers

2011 IEEE GCC Conference and Exhibition (GCC), 2011, p.617-620

2011

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Low Power Implementation of Digital Filters using DBNS Representation and Sub-expression Sharing

2008 2nd International Conference on Signals, Circuits and Systems, 2008, p.1-6

2008

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Evaluation of FIR filters implementations for low power multistandard receivers

5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2010, p.1-5

2010

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Low Power Implementation of Decimation Filters in Multistandard Radio Receiver Using Optimized Multiplication-Accumulation Unit

2007 14th IEEE International Conference on Electronics, Circuits and Systems, 2007, p.1183-1186

2007

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Low power FPGA-based implementation of decimating filters for multistandard receiver

International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006, 2006, p.10-14

2006

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Low Power Design of a Decimation Filter in Multi-Standard Receiver

2008 3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2008, p.1-5

2008

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Hardware design of Euclidean Projection modules for ADMM LDPC decoding

Design of a reconfigurable digital decimation filter for flexible GNSS receivers

A survey on decoding schedules of LDPC convolutional codes and associated hardware architectures

Comparison of different schedulings for the ADMM based LDPC decoding

Implementation aspects of a pipeline ADMM-based LP decoding of LDPC convolutional codes

ADMM hardware decoder for regular LDPC codes using a NISC-based architecture

Multicore implementation of LDPC decoders based on ADMM algorithm

A Comparative Evaluation of Well-known Feature Extractors for Multi-view Vehicle Tracking in VSNs

Deep Multi-modal Object Detection for Autonomous Driving

Feature-based Vehicle Tracking at Roundabouts in Visual Sensor Networks

Design and Implementation of a Reconfigurable Decimation and Channel Selection Filter for GSM and UMTS Radio Standards

Low complexity ADMM-LP based decoding strategy for LDPC convolutional codes

Reduced complexity ADMM-based schedules for LP decoding of LDPC convolutional codes

Hardware complexity reduction of LDPC-CC decoders based on message-passing approaches

An LP-based algorithm for decoding terminated LDPC convolutional codes

A reconfigurable Digital Down Converter architecture for multistandard GNSS receiver

Analysis of ADMM-LP algorithm for LDPC decoding, a first step to hardware implementation

Experiments on designing low power decimation filter for multistandard receiver on heterogeneous targets

Power consumption estimation models for FIR decimation filters in multi-standard receivers

Low Power Implementation of Digital Filters using DBNS Representation and Sub-expression Sharing

Evaluation of FIR filters implementations for low power multistandard receivers

Low Power Implementation of Decimation Filters in Multistandard Radio Receiver Using Optimized Multiplication-Accumulation Unit

Low power FPGA-based implementation of decimating filters for multistandard receiver

Low Power Design of a Decimation Filter in Multi-Standard Receiver

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