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Future Generation Information Technology: 4th International Conference, FGIT 2012, Gangneug, Korea, December 16-19, 2012. Proceedings

1, 2012

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A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.206-208

2018

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13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.238-240

2024

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A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.204-206

2018

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A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization

2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, Vol.65, p.444-446

2022

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Radar target identification using a DTV-based passive radar in South Korea

2017 Progress in Electromagnetics Research Symposium - Fall (PIERS - FALL), 2017, p.892-895

2017

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A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022, p.130-131

2022

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A 5G mm-Wave Single Chip 8-channel FEM with Best-in-class 22% Power Efficiency and Embedded Die Substrate (EDS) Technology

2021 IEEE MTT-S International Microwave Symposium (IMS), 2021, p.721-724

2021

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Two-photon probes for pH: Detection of human colon cancer using two-photon microscopy

Journal of clinical oncology, 2018, Vol.36 (4_suppl), p.607-607

2018

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8Gb 3D DDR3 DRAM using through-silicon-via technology

2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009, p.130-131,131a

2009

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13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.234-236

2024

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A Highly Linear 28GHz 16-Element Phased-Array Receiver with Wide Gain Control for 5G NR Application

2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2019, p.287-290

2019

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A Performance Comparison on the Machine Learning Classifiers in Predictive Pathology Staging of Prostate Cancer

Studies in health technology and informatics, 2017, Vol.245, p.1273

2017

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Prioritized energy optimal management for home-to-home in smart grid

2017 IEEE International Conference on Consumer Electronics (ICCE), 2017, p.321-322

2017

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Comparison of Energy Efficiency Policy for Old Buildings Focusing on Korea

2023 8th International Conference on Smart and Sustainable Technologies (SpliTech), 2023, p.1-5

2023

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Endoscopic Spine Procedures

Daniel H. Kim, Gun Choi

2011

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22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST

2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020, p.334-336

2020

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An IEEE 802.15.4g SUN OFDM-based RF CMOS transceiver for Smart Grid and CEs

2013 IEEE International Conference on Consumer Electronics (ICCE), 2013, p.520-521

2013

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Development and Evaluation of SHGC Measurement System for Cooling Energy Saving in Buildings

Advanced materials research, 2013, Vol.689, p.176-179

2013

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Energy Performance Assessment of the High Insulated Panels Green Home

Advanced materials research, 2013, Vol.689, p.394-397

2013

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The Preparation of Primary Battery Separator Using Polyamide Nonwoven and Nanofiber

Advanced materials research, 2013, Vol.724-725, p.1079-1082

2013

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5.5 A 2.1e− Temporal Noise and −105dB Parasitic Light Sensitivity Backside-Illuminated 2.3µm-Pixel Voltage-Domain Global Shutter CMOS Image Sensor Using High-Capacity DRAM Capacitor Technology

2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020, p.102-104

2020

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3-Layer Stacked Voltage-Domain Global Shutter CMOS Image Sensor with 1.8μm-Pixel-Pitch

2022 International Electron Devices Meeting (IEDM), 2022, p.37.5.1-37.5.4

2022

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A new guard-ring technique to reduce coupling noise from through silicon via (TSV) utilizing inversion charge induced by interface charge

2013 Symposium on VLSI Technology, 2013, p.T44-T45

2013

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23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme

2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, p.390-391

2017

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Future Generation Information Technology: 4th International Conference, FGIT 2012, Gangneug, Korea, December 16-19, 2012. Proceedings

A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process

13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization

A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking

A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization

Radar target identification using a DTV-based passive radar in South Korea

A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features

A 5G mm-Wave Single Chip 8-channel FEM with Best-in-class 22% Power Efficiency and Embedded Die Substrate (EDS) Technology

Two-photon probes for pH: Detection of human colon cancer using two-photon microscopy

8Gb 3D DDR3 DRAM using through-silicon-via technology

13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process

A Highly Linear 28GHz 16-Element Phased-Array Receiver with Wide Gain Control for 5G NR Application

A Performance Comparison on the Machine Learning Classifiers in Predictive Pathology Staging of Prostate Cancer

Prioritized energy optimal management for home-to-home in smart grid

Comparison of Energy Efficiency Policy for Old Buildings Focusing on Korea

Endoscopic Spine Procedures

22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST

An IEEE 802.15.4g SUN OFDM-based RF CMOS transceiver for Smart Grid and CEs

Development and Evaluation of SHGC Measurement System for Cooling Energy Saving in Buildings

Energy Performance Assessment of the High Insulated Panels Green Home

The Preparation of Primary Battery Separator Using Polyamide Nonwoven and Nanofiber

5.5 A 2.1e− Temporal Noise and −105dB Parasitic Light Sensitivity Backside-Illuminated 2.3µm-Pixel Voltage-Domain Global Shutter CMOS Image Sensor Using High-Capacity DRAM Capacitor Technology

3-Layer Stacked Voltage-Domain Global Shutter CMOS Image Sensor with 1.8μm-Pixel-Pitch

A new guard-ring technique to reduce coupling noise from through silicon via (TSV) utilizing inversion charge induced by interface charge

23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme

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