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7.9 1/2.74-inch 32Mpixel-Prototype CMOS Image Sensor with 0.64μ m Unit Pixels Separated by Full-Depth Deep-Trench Isolation

2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, Vol.64, p.122-124

2021

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Properties of isolation liner and electrical characteristics of high aspect ratio TSV in 3D stacking technology

2012 SEMI Advanced Semiconductor Manufacturing Conference, 2012, p.198-200

2012

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A non-linear ReRAM cell with sub-1μA ultralow operating current for high density vertical resistive memory (VRRAM)

2012 International Electron Devices Meeting, 2012, p.20.8.1-20.8.4

2012

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A practical Si nanowire technology with nanowire-on-insulator structure for beyond 10nm logic technologies

2013 IEEE International Electron Devices Meeting, 2013, p.26.5.1-26.5.4

2013

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The Enhancement of Etch Rate of Silicon by Heavy Doping of Phosphorus and Arsenic Atoms during Cyclic Selective Epitaxial Growth of Silicon

ECS transactions, 2012, Vol.45 (6), p.49-54

2012

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Integration Friendly Dual Metal Gate Technology Using Dual Thickness Metal Inserted Poly-Si Stacks (DT-MIPS)

2007 IEEE Symposium on VLSI Technology, 2007, p.196-197

2007

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Current-voltage characteristics of vertical diodes for next generation memories

2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2012, p.149-152

2012

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Heterogeneous Integration of O-band LDs on bulk-Si Platform

2019 24th OptoElectronics and Communications Conference (OECC) and 2019 International Conference on Photonics in Switching and Computing (PSC), 2019, p.1-3

2019

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Heterogeneously integrated ligtht sources on bulk-silicon platform

2018 IEEE International Electron Devices Meeting (IEDM), 2018, p.23.6.1-23.6.4

2018

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Annealing process and structural considerations in controlling extrusion-type defects Cu TSV

2012 IEEE International Interconnect Technology Conference, 2012, p.1-3

2012

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Multi-domain process modeling for advanced logic and memory devices: from equimpments to materials

2018 IEEE International Electron Devices Meeting (IEDM), 2018, p.33.4.1-33.4.4

2018

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Novel flowable CVD process technology for sub-20nm interlayer dielectrics

2012 IEEE International Interconnect Technology Conference, 2012, p.1-3

2012

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Highly reliable ReRAM technology with encapsulation process for 20nm and beyond

2013 5th IEEE International Memory Workshop, 2013, p.42-43

2013

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Successful recovery of moisture-induced TDDB degradation for Cu/ULK(k=2.5) BEOL interconnect

2012 IEEE International Interconnect Technology Conference, 2012, p.1-3

2012

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Robust porous SiOCH (k=2.5) for 28nm and beyond technology node

2011 IEEE International Interconnect Technology Conference, 2011, p.1-3

2011

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Mass Production Worthy MIM Capacitor On Gate polysilicon(MIM-COG) Structure using HfO2/HfOxCyNz/HfO2 Dielectric for Analog/RF/Mixed Signal Application

2007 IEEE International Electron Devices Meeting, 2007, p.993-996

2007

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DAC technologist panel "the IC nanometer race - what will it take to win"

2006 43rd ACM/IEEE Design Automation Conference, 2006, p.77-78

2006

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PBTI & HCI characteristics for high-k gate dielectrics with poly-Si & MIPS (metal inserted poly-Si stack) gates

2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual, 2005, p.50-54

2005

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Breakdown and conduction mechanisms of ALD HfSiON dielectric with TaN gate using carrier separation analysis [MOSFETs]

2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual, 2005, p.630-631

2005

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Reliable integration of robust porous ultra low-k (ULK) for the advanced BEOL interconnect

2013 IEEE International Interconnect Technology Conference - IITC, 2013, p.1-3

2013

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5.6 A 1/2.65in 44Mpixel CMOS Image Sensor with 0.7µm Pixels Fabricated in Advanced Full-Depth Deep-Trench Isolation Technology

2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020, p.104-106

2020

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5.5 A 2.1e− Temporal Noise and −105dB Parasitic Light Sensitivity Backside-Illuminated 2.3µm-Pixel Voltage-Domain Global Shutter CMOS Image Sensor Using High-Capacity DRAM Capacitor Technology

2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020, p.102-104

2020

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New insight into stress induced voiding mechanism in Cu interconnects

Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005, 2005, p.108-110

2005

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Highly Manufacturable Single Metal Gate Process Using Ultra-Thin Metal Inserted Poly-Si Stack (UT-MIPS)

2006 International Electron Devices Meeting, 2006, p.1-4

2006

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Essays on macro-finance asset pricing models and estimation

Kang, Kyu Ho

2010

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7.9 1/2.74-inch 32Mpixel-Prototype CMOS Image Sensor with 0.64μ m Unit Pixels Separated by Full-Depth Deep-Trench Isolation

Properties of isolation liner and electrical characteristics of high aspect ratio TSV in 3D stacking technology

A non-linear ReRAM cell with sub-1μA ultralow operating current for high density vertical resistive memory (VRRAM)

A practical Si nanowire technology with nanowire-on-insulator structure for beyond 10nm logic technologies

The Enhancement of Etch Rate of Silicon by Heavy Doping of Phosphorus and Arsenic Atoms during Cyclic Selective Epitaxial Growth of Silicon

Integration Friendly Dual Metal Gate Technology Using Dual Thickness Metal Inserted Poly-Si Stacks (DT-MIPS)

Current-voltage characteristics of vertical diodes for next generation memories

Heterogeneous Integration of O-band LDs on bulk-Si Platform

Heterogeneously integrated ligtht sources on bulk-silicon platform

Annealing process and structural considerations in controlling extrusion-type defects Cu TSV

Multi-domain process modeling for advanced logic and memory devices: from equimpments to materials

Novel flowable CVD process technology for sub-20nm interlayer dielectrics

Highly reliable ReRAM technology with encapsulation process for 20nm and beyond

Successful recovery of moisture-induced TDDB degradation for Cu/ULK(k=2.5) BEOL interconnect

Robust porous SiOCH (k=2.5) for 28nm and beyond technology node

Mass Production Worthy MIM Capacitor On Gate polysilicon(MIM-COG) Structure using HfO2/HfOxCyNz/HfO2 Dielectric for Analog/RF/Mixed Signal Application

DAC technologist panel "the IC nanometer race - what will it take to win"

PBTI & HCI characteristics for high-k gate dielectrics with poly-Si & MIPS (metal inserted poly-Si stack) gates

Breakdown and conduction mechanisms of ALD HfSiON dielectric with TaN gate using carrier separation analysis [MOSFETs]

Reliable integration of robust porous ultra low-k (ULK) for the advanced BEOL interconnect

5.6 A 1/2.65in 44Mpixel CMOS Image Sensor with 0.7µm Pixels Fabricated in Advanced Full-Depth Deep-Trench Isolation Technology

5.5 A 2.1e− Temporal Noise and −105dB Parasitic Light Sensitivity Backside-Illuminated 2.3µm-Pixel Voltage-Domain Global Shutter CMOS Image Sensor Using High-Capacity DRAM Capacitor Technology

New insight into stress induced voiding mechanism in Cu interconnects

Highly Manufacturable Single Metal Gate Process Using Ultra-Thin Metal Inserted Poly-Si Stack (UT-MIPS)

Essays on macro-finance asset pricing models and estimation

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