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Versatile Transition-Time Monitoring for Interconnects via Distributed TDC
IEEE design and test, 2016-12, Vol.33 (6), p.23-30
2016
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JARVA: Joint Application-Aware Oblivious Routing and Static Virtual Channel Allocation
IEEE design and test, 2022-12, Vol.39 (6), p.16-27
2022
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Scan Integrity Tests for EDT Compression
IEEE design and test, 2020-08, Vol.37 (4), p.21-26
2020
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Automated Probe-Mark Analysis for Advanced Probe Technology Characterization
IEEE design and test, 2021-10, Vol.38 (5), p.82-89
2021
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A DVFS Design and Simulation Framework Using Machine Learning Models
IEEE design and test, 2023-02, Vol.40 (1), p.52-61
2023
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Compact Modeling of Thin-Film Transistors for Flexible Hybrid IoT Design
IEEE design and test, 2019-08, Vol.36 (4), p.6-14
2019
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Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package
IEEE design and test, 2017-06, Vol.34 (3), p.50-58
2017
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Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement
IEEE design and test, 2016-04, Vol.33 (2), p.30-39
2016
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Delay Characterization and Testing of Arbitrary Multiple-Pin Interconnects
IEEE design and test, 2016-04, Vol.33 (2), p.9-16
2016
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Built-In Self-Test/Repair Methodology for Multiband RF-Interconnected TSV 3D Integration
IEEE design and test, 2019-12, Vol.36 (6), p.63-71
2019
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A Fast and Jitter-Modulation Free Jitter Tolerance Estimation Technique for Bang- Bang CDRs
IEEE design and test, 2018-02, Vol.35 (1), p.63-73
2018
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Detecting and Scoring Equipment Faults in Real Time During Semiconductor Test Processes
IEEE design and test, 2021-08, Vol.38 (4), p.119-126
2021
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Controller Architecture for Low-Power, Low-Latency DRAM With Built-in Cache
IEEE design and test, 2017-04, Vol.34 (2), p.69-78
2017
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Voltage-Resistance-Adaptive MPPT Circuit for Energy Harvesting
IEEE design and test, 2024-06, Vol.41 (3), p.54-62
2024
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Computing-In-Memory Using Ferroelectrics: From Single- to Multi-Input Logic
IEEE design and test, 2022-04, Vol.39 (2), p.56-64
2022
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On Improving Interconnect Defect Diagnosis Resolution and Yield for Interposer-Based 3-D ICs
IEEE design and test, 2014-08, Vol.31 (4), p.16-26
2014
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Layout-Aware Optimized Prebond Silicon Interposer Test Synthesis
IEEE design and test, 2017-12, Vol.34 (6), p.77-83
2017
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Measuring System Design and Experimental Research on Electrostatic Attractive Force
IEEE design and test, 2018-12, Vol.35 (6), p.71-77
2018
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An Energy-Efficient Silicon Microring Resonator-Based Photonic Transmitter
IEEE design and test, 2014-10, Vol.31 (5), p.46-54
2014
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Statistical Variability and Reliability and the Impact on Corresponding 6T-SRAM Cell Design for a 14-nm Node SOI FinFET Technology
IEEE design and test, 2013-12, Vol.30 (6), p.18-28
2013
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Intellectual Property Protection of Deep Learning Systems via Hardware/Software Co-design
IEEE design and test, 2024-04, Vol.41 (2), p.1-1
2024
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Identifying Systematic Failures on Semiconductor Wafers Using ADCAS
IEEE design and test, 2013-10, Vol.30 (5), p.44-53
2013
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