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Optimal buffered compression and coding mode selection for MPEG-4 shape coding

IEEE transactions on image processing, 2001-05, Vol.10 (5), p.686-700

2001

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Peripheral vision function training contents for people with low vision with Python tkinter

2022 13th International Conference on Information and Communication Technology Convergence (ICTC), 2022, p.739-741

2022

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A functional design for smart glasses for low vision people that provides visual assistance based on various image processing technologies

2022 International Conference on Electronics, Information, and Communication (ICEIC), 2022, p.1-3

2022

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A/C Load Forecasting Using Deep Learning

2017 International Conference on Computational Science and Computational Intelligence (CSCI), 2017, p.1840-1841

2017

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Prediction of 4-year risk for coronary artery calcification using ensemble-based classification

2013 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2013, Vol.2013, p.3210-3213

2013

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Optimal shape coding under buffer constraints

Proceedings 1998 International Conference on Image Processing. ICIP98 (Cat. No.98CB36269), 1998, Vol.1, p.290-294 vol.1

1998

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Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM

IEEE journal of solid-state circuits, 2018-10, Vol.53 (10), p.2906-2916

2018

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A 90 nm 1.8 V 512 Mb Diode-Switch PRAM With 266 MB/s Read Throughput

IEEE journal of solid-state circuits, 2008-01, Vol.43 (1), p.150-162

2008

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JumpRoACH: A Trajectory-Adjustable Integrated Jumping-Crawling Robot

IEEE/ASME transactions on mechatronics, 2019-06, Vol.24 (3), p.947-958

2019

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Agile and Energy-Efficient Jumping-Crawling Robot Through Rapid Transition of Locomotion and Enhanced Jumping Height Adjustment

IEEE/ASME transactions on mechatronics, 2022-12, Vol.27 (6), p.5890-5901

2022

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Method to Achieve the Morphotropic Phase Boundary in HfxZr1−xO2 by Electric Field Cycling for DRAM Cell Capacitor Applications

IEEE electron device letters, 2021-04, Vol.42 (4), p.517-520

2021

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A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme

IEEE journal of solid-state circuits, 2021-01, Vol.56 (1), p.199-211

2021

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256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers

IEEE journal of solid-state circuits, 2017-01, Vol.52 (1), p.210-217

2017

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Design of High-End Synchronous Reluctance Motor Using 3-D Printing Technology

IEEE transactions on magnetics, 2017-06, Vol.53 (6), p.1-5

2017

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A 1.05-A/m Minimum Magnetic Field Strength Single-Chip, Fully Integrated Biometric Smart Card SoC Achieving 792.5-ms Transaction Time With Anti-Spoofing Fingerprint Authentication

IEEE journal of solid-state circuits, 2023-01, Vol.58 (1), p.1-12

2023

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Ultralow- k Amorphous Boron Nitride Film for Copper Interconnect Capping Layer

IEEE transactions on electron devices, 2023-05, Vol.70 (5), p.2588-2593

2023

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25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications

2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, Vol.64, p.350-352

2021

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An Islanding Detection Method for Multi-RES Systems Using the Graph Search Method

IEEE transactions on sustainable energy, 2020-10, Vol.11 (4), p.2722-2731

2020

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A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking

IEEE journal of solid-state circuits, 2019-01, Vol.54 (1), p.197-209

2019

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Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory

2009 Symposium on VLSI Technology, 2009, p.192-193

2009

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A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.204-206

2018

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A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation

IEEE journal of solid-state circuits, 2015-01, Vol.50 (1), p.178-190

2015

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First Demonstration of Junctionless Accumulation-Mode Bulk FinFETs With Robust Junction Isolation

IEEE electron device letters, 2013-12, Vol.34 (12), p.1479-1481

2013

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A 16Gb/s/pin 8Gb GDDR6 DRAM with bandwidth extension techniques for high-speed applications

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.210-212

2018

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An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion

IEEE journal of solid-state circuits, 2008-01, Vol.43 (1), p.121-131, Article 121

2008

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Optimal buffered compression and coding mode selection for MPEG-4 shape coding

Peripheral vision function training contents for people with low vision with Python tkinter

A functional design for smart glasses for low vision people that provides visual assistance based on various image processing technologies

A/C Load Forecasting Using Deep Learning

Prediction of 4-year risk for coronary artery calcification using ensemble-based classification

Optimal shape coding under buffer constraints

Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM

A 90 nm 1.8 V 512 Mb Diode-Switch PRAM With 266 MB/s Read Throughput

JumpRoACH: A Trajectory-Adjustable Integrated Jumping-Crawling Robot

Agile and Energy-Efficient Jumping-Crawling Robot Through Rapid Transition of Locomotion and Enhanced Jumping Height Adjustment

Method to Achieve the Morphotropic Phase Boundary in HfxZr1−xO2 by Electric Field Cycling for DRAM Cell Capacitor Applications

A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme

256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers

Design of High-End Synchronous Reluctance Motor Using 3-D Printing Technology

A 1.05-A/m Minimum Magnetic Field Strength Single-Chip, Fully Integrated Biometric Smart Card SoC Achieving 792.5-ms Transaction Time With Anti-Spoofing Fingerprint Authentication

Ultralow- k Amorphous Boron Nitride Film for Copper Interconnect Capping Layer

25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications

An Islanding Detection Method for Multi-RES Systems Using the Graph Search Method

A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking

Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory

A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking

A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation

First Demonstration of Junctionless Accumulation-Mode Bulk FinFETs With Robust Junction Isolation

A 16Gb/s/pin 8Gb GDDR6 DRAM with bandwidth extension techniques for high-speed applications

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion

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