UB Paderborn / Katalog / Suche / in CDI

Measuring the Gap Between FPGAs and ASICs

IEEE transactions on computer-aided design of integrated circuits and systems, 2007-02, Vol.26 (2), p.203-215

2007

Link zum Volltext
IEEE_Xplore

Analytical Die-to-Die 3-D Placement With Bistratal Wirelength Model and GPU Acceleration

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-06, Vol.43 (6), p.1624-1637

2024

Link zum Volltext
IEEE_Xplore

OMNI: A Framework for Integrating Hardware and Software Optimizations for Sparse CNNs

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-08, Vol.40 (8), p.1648-1661

2021

Link zum Volltext

Verfügbarkeit prüfen

Anti-SAT: Mitigating SAT Attack on Logic Locking

IEEE transactions on computer-aided design of integrated circuits and systems, 2019-02, Vol.38 (2), p.199-207

2019

Link zum Volltext
IEEE_Xplore

Accurate Simulation of High-Gain MMIC Amplifiers With Microstrip-Type Transistors

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-01, Vol.42 (1), p.16-26

2023

Link zum Volltext
IEEE_Xplore

Analytical Die-to-Die 3D Placement With Bistratal Wirelength Model and GPU Acceleration

IEEE transactions on computer-aided design of integrated circuits and systems, 2023, p.1-1

2023

Link zum Volltext

Verfügbarkeit prüfen

An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-05, Vol.41 (5), p.1209-1221

2022

Link zum Volltext
IEEE_Xplore

AccelTran: A Sparsity-Aware Accelerator for Dynamic Inference with Transformers

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-11, Vol.42 (11), p.1-1

2023

Link zum Volltext
IEEE_Xplore

Analog and Mixed-Signal IC Security via Sizing Camouflaging

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-05, Vol.40 (5), p.822-835

2021

Link zum Volltext
IEEE_Xplore

A Machine Learning-Powered Tier Partitioning Methodology for Monolithic 3-D ICs

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-11, Vol.41 (11), p.4575-4586

2022

Link zum Volltext
IEEE_Xplore

TSV-Based 3-D ICs: Design Methods and Tools

IEEE transactions on computer-aided design of integrated circuits and systems, 2017-10, Vol.36 (10), p.1593-1619

2017

Link zum Volltext
IEEE_Xplore

TransCODE: Co-design of Transformers and Accelerators for Efficient Training and Inference

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-12, Vol.42 (12), p.1-1

2023

Link zum Volltext
IEEE_Xplore

An Artificial Neural Network Assisted Optimization System for Analog Design Space Exploration

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-10, Vol.39 (10), p.2640-2653

2020

Link zum Volltext
IEEE_Xplore

Highly Efficient Automatic Synthesis of a Millimeter-Wave On-Chip Deformable Spiral Inductor Using a Hybrid Knowledge-Guided and Data-Driven Technique

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-12, Vol.42 (12), p.1-1

2023

Link zum Volltext
IEEE_Xplore

MURLAV: A Multiple-Node-Upset Recovery Latch and Algorithm-Based Verification Method

IEEE transactions on computer-aided design of integrated circuits and systems, 2024, p.1-1

2024

Link zum Volltext

Verfügbarkeit prüfen

XBarNet: Computationally Efficient Memristor Crossbar Model Using Convolutional Autoencoder

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-12, Vol.41 (12), p.5489-5500

2022

Link zum Volltext
IEEE_Xplore

A Cost-Effective TSV Repair Architecture for Clustered Faults in 3-D IC

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-09, Vol.40 (9), p.1952-1956

2021

Link zum Volltext
IEEE_Xplore

Golden-Free Robust Age Estimation to Triage Recycled ICs

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-09, Vol.42 (9), p.1-1

2023

Link zum Volltext
IEEE_Xplore

On Legalization of Die Bonding Bumps and Pads for 3D ICs

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-03, p.1-1

2024

Link zum Volltext
IEEE_Xplore

LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-10, Vol.39 (10), p.2938-2951

2020

Link zum Volltext
IEEE_Xplore

Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop

IEEE transactions on computer-aided design of integrated circuits and systems, 2019-06, Vol.38 (6), p.989-1002

2019

Link zum Volltext
IEEE_Xplore

The Detection of Open and Leakage Faults for Prebond TSV Test Based on Weak Current Source

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-09, Vol.41 (9), p.2768-2779

2022

Link zum Volltext
IEEE_Xplore

QuCTS-Single-Flux Quantum Clock Tree Synthesis

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-10, Vol.41 (10), p.3346-3358

2022

Link zum Volltext
IEEE_Xplore

MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-10, Vol.41 (10), p.3162-3181

2022

Link zum Volltext

Verfügbarkeit prüfen

Modeling the Dependency of Analog Circuit Performance Parameters on Manufacturing Process Variations With Applications in Sensitivity Analysis and Yield Prediction

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-01, Vol.41 (1), p.129-142

2022

Link zum Volltext
IEEE_Xplore

Menü

Weitere Dienste

Einstellungen

Measuring the Gap Between FPGAs and ASICs

Analytical Die-to-Die 3-D Placement With Bistratal Wirelength Model and GPU Acceleration

OMNI: A Framework for Integrating Hardware and Software Optimizations for Sparse CNNs

Anti-SAT: Mitigating SAT Attack on Logic Locking

Accurate Simulation of High-Gain MMIC Amplifiers With Microstrip-Type Transistors

Analytical Die-to-Die 3D Placement With Bistratal Wirelength Model and GPU Acceleration

An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization

AccelTran: A Sparsity-Aware Accelerator for Dynamic Inference with Transformers

Analog and Mixed-Signal IC Security via Sizing Camouflaging

A Machine Learning-Powered Tier Partitioning Methodology for Monolithic 3-D ICs

TSV-Based 3-D ICs: Design Methods and Tools

TransCODE: Co-design of Transformers and Accelerators for Efficient Training and Inference

An Artificial Neural Network Assisted Optimization System for Analog Design Space Exploration

Highly Efficient Automatic Synthesis of a Millimeter-Wave On-Chip Deformable Spiral Inductor Using a Hybrid Knowledge-Guided and Data-Driven Technique

MURLAV: A Multiple-Node-Upset Recovery Latch and Algorithm-Based Verification Method

XBarNet: Computationally Efficient Memristor Crossbar Model Using Convolutional Autoencoder

A Cost-Effective TSV Repair Architecture for Clustered Faults in 3-D IC

Golden-Free Robust Age Estimation to Triage Recycled ICs

On Legalization of Die Bonding Bumps and Pads for 3D ICs

LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults

Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop

The Detection of Open and Leakage Faults for Prebond TSV Test Based on Weak Current Source

QuCTS-Single-Flux Quantum Clock Tree Synthesis

MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper

Modeling the Dependency of Analog Circuit Performance Parameters on Manufacturing Process Variations With Applications in Sensitivity Analysis and Yield Prediction

Aktive Filter

Suchergebnisse filtern