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A 0.0016 mm² 0.64 nJ leakage-based CMOS temperature sensor

Sensors (Basel, Switzerland), 2013-09, Vol.13 (9), p.12648-12662

2013

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A 0.0025mm2 8-bit 70MS/s SAR ADC with a Linearity-Improved Bootstrapped Switch for Computation in Memory

2023 8th International Conference on Integrated Circuits and Microsystems (ICICM), 2023, p.412-416

2023

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A 0.007 mm2 0.6 V 6 MS/s Low-Power Double Rail-to-Rail SAR ADC in 65-nm CMOS

IEEE transactions on circuits and systems. II, Express briefs, 2021-09, Vol.68 (9), p.3088-3092

2021

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A 0.021 µm2 trigate SRAM cell with aggressively scaled gate and contact pitch

2011 Symposium on VLSI Technology - Digest of Technical Papers, 2011, p.64-65

2011

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A 0.02mm super(2) embedded temperature sensor with plus or minus 2 degree C inaccuracy for self-refresh control in 25nm mobile DRAM

Proceedings of ESSCIRC, 2015-09, p.267-270

2015

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A 0.02mm2 embedded temperature sensor with ±2°C inaccuracy for self-refresh control in 25nm mobile DRAM

ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC), 2015, p.267-270

2015

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A 0.05×0.05mm2 RFID Chip with Easily Scaled-Down ID-Memory

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007, p.482-483

2007

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A 0.05- ^ 2.91-nJ/Decision Keyword-Spotting (KWS) Chip Featuring an Always-Retention 5T-SRAM in 28-nm CMOS

IEEE journal of solid-state circuits, 2023-07, p.1-10

2023

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A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

2010 Symposium on VLSI Technology, 2010, p.19-20

2010

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A 0.078 pJ/SOP Unstructured Sparsity-Aware Spiking Attention/Convolution Processor with 3D Compute Array

2024 IEEE Custom Integrated Circuits Conference (CICC), 2024, p.1-2

2024

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A 0.08 /spl mu/m/sup 2/-sized 8F/sup 2/ stack DRAM cell for multi-gigabit DRAM

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303), 2002, p.56-57

2002

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A 0.086-mm ^2 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28-nm CMOS

IEEE transactions on biomedical circuits and systems, 2019-02, Vol.13 (1), p.145-158

2019

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A 0.08μm2-sized 8F2 Stack DRAM cell for multi-gigabit DRAM

2002

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A 0.094um super(2) high density and aging resilient 8T SRAM with 14nm FinFET technology featuring 560mV V sub(MIN) with read and write assist

2015 Symposium on VLSI Circuits (VLSI Circuits), 2015-06, p.C266-C267

2015

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A 0.094um2 high density and aging resilient 8T SRAM with 14nm FinFET technology featuring 560mV VMIN with read and write assist

2015 Symposium on VLSI Circuits (VLSI Circuits), 2015, p.C266-C267

2015

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A 0-1 Integer Linear Programming Based Approach for Global Locality Optimizations

Advances in Computer Systems Architecture, p.281-294

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A 0.1- \mu} 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation

IEEE journal of solid-state circuits, 2007-01, Vol.42 (1), p.210-218

2007

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A 0.1/spl mu/A standby current, bouncing-noise-immune 1Mb SRAM

Symposium 1988 on VLSI Circuits, 1988, p.49-50

1988

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A 0.1/spl mu/m 1.8V 256Mb 66MHz Synchronous Burst PRAM

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers, 2006, p.487-496

2006

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0.1 /spl mu/m-rule MRAM development using double-layered hard mask

International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224), 2001, p.36.4.1-36.4.4

2001

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A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008, p.282-613

2008

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A 0.1-υA standby current, ground-bounce-immune 1-Mbit CMOS SRAM

IEEE journal of solid-state circuits, 1989, Vol.24 (6), p.1708-1713

1989

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A 0.11 /spl mu/m DRAM technology for 4Gb DRAM and beyond

2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443), 2001, Vol.1, p.178-182 vol.1

2001

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A 0.115 /spl mu/m/sup 2/ 8F/sup 2/ DRAM working cell with LPRD (low parasitic resistance device) and poly metal gate technology for gigabit DRAM

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184), 2001, p.25-26

2001

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0.12 /spl mu/m hole pattern formation by KrF lithography for Giga bit DRAM

International Electron Devices Meeting. Technical Digest, 1996, p.61-64

1996

Volltextzugriff (PDF)

1 – 25 von 318.319

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A 0.0016 mm² 0.64 nJ leakage-based CMOS temperature sensor

A 0.0025mm2 8-bit 70MS/s SAR ADC with a Linearity-Improved Bootstrapped Switch for Computation in Memory

A 0.007 mm2 0.6 V 6 MS/s Low-Power Double Rail-to-Rail SAR ADC in 65-nm CMOS

A 0.021 µm2 trigate SRAM cell with aggressively scaled gate and contact pitch

A 0.02mm super(2) embedded temperature sensor with plus or minus 2 degree C inaccuracy for self-refresh control in 25nm mobile DRAM

A 0.02mm2 embedded temperature sensor with ±2°C inaccuracy for self-refresh control in 25nm mobile DRAM

A 0.05×0.05mm2 RFID Chip with Easily Scaled-Down ID-Memory

A 0.05- ^ 2.91-nJ/Decision Keyword-Spotting (KWS) Chip Featuring an Always-Retention 5T-SRAM in 28-nm CMOS

A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

A 0.078 pJ/SOP Unstructured Sparsity-Aware Spiking Attention/Convolution Processor with 3D Compute Array

A 0.08 /spl mu/m/sup 2/-sized 8F/sup 2/ stack DRAM cell for multi-gigabit DRAM

A 0.086-mm ^2 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28-nm CMOS

A 0.08μm2-sized 8F2 Stack DRAM cell for multi-gigabit DRAM

A 0.094um super(2) high density and aging resilient 8T SRAM with 14nm FinFET technology featuring 560mV V sub(MIN) with read and write assist

A 0.094um2 high density and aging resilient 8T SRAM with 14nm FinFET technology featuring 560mV VMIN with read and write assist

A 0-1 Integer Linear Programming Based Approach for Global Locality Optimizations

A 0.1- \mu} 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation

A 0.1/spl mu/A standby current, bouncing-noise-immune 1Mb SRAM

A 0.1/spl mu/m 1.8V 256Mb 66MHz Synchronous Burst PRAM

0.1 /spl mu/m-rule MRAM development using double-layered hard mask

A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology

A 0.1-υA standby current, ground-bounce-immune 1-Mbit CMOS SRAM

A 0.11 /spl mu/m DRAM technology for 4Gb DRAM and beyond

A 0.115 /spl mu/m/sup 2/ 8F/sup 2/ DRAM working cell with LPRD (low parasitic resistance device) and poly metal gate technology for gigabit DRAM

0.12 /spl mu/m hole pattern formation by KrF lithography for Giga bit DRAM

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