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The Reliability and Noise Investigation of Boron Diffusion Under Positive Bias Temperature Instability in 16 nm Node High Voltage FinFETs

IEEE transactions on electron devices, 2024-10, p.1-6

2024

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3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM With Leakage Saving Circuits in 3-nm FinFET for HPC Applications

IEEE journal of solid-state circuits, 2024-08, p.1-9

2024

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High-Temperature Retention Stability of Multibit Ferroelectric HfZrO₂ FinFET With SiGe/Si Superlattice Channel for Enhanced Speed and Memory Window

IEEE transactions on electron devices, 2024-10, Vol.71 (10), p.5975-5979

2024

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Optimization of Multi-fins FinFET Implemented on SOI Wafer Based on SiGe and Gaussian Process Regression

IEEE access, 2024-11, p.1-1

2024

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Improved Electrical Characteristics of Ge FinFET CMOS by Plasma-Enhanced Oxidation and Partial Nitridation with Supercritical Fluid Treatment

IEEE electron device letters, 2024-10, p.1-1

2024

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A 4-mW 2.2-6.9 GHz LNA in 16 nm FinFET Technology for Cryogenic Applications

IEEE microwave and wireless technology letters (Print), 2024-10, p.1-4

2024

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Understanding the Self-Heating Effects Measured With the AC Output Conductance Method in Advanced FinFET Nodes

IEEE transactions on electron devices, 2024-11, Vol.71 (11), p.6976-6982

2024

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Self-Heating Effect Analysis and Characterization of 6T SRAM Based on Delay Variation

IEEE transactions on electron devices, 2024-10, p.1-8

2024

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Cryogenic Temperature Effects on 16nm FinFet Performance and Mismatch

2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 2024, p.341-344

2024

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Synthesizable 10-bit Stochastic TDC Using Common-Mode Time Dithering and Passive Approximate Adder with 0.012mm2 Active Area in 12nm FinFET

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2

2024

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CAPE: Criticality-Aware Performance and Energy Optimization Policy for NCFET-Based Caches

IEEE transactions on computers, 2024-12, Vol.73 (12), p.2830-2843

2024

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Elevated-Epi (Elepi) Technique for 3D IC With Stacked FinFETs, Interlevel Metal, and 25 \times 33 mm ^} Single-Crystalline Silicon on SiO \text

IEEE transactions on electron devices, 2024-10, p.1-6

2024

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Millimeter-Wave CMOS Devices Design With Mobility Enhancement and Parasitic RC Suppression for Super-350 GHz \textit} and \textit} in Multiring nMOSFETs

IEEE transactions on electron devices, 2024-11, p.1-7

2024

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Analyzing the Influence of Source/Drain Growth Height and Lateral Growth Depth in FinFETs Through XGBoost and SHAP

IEEE electron device letters, 2024-10, Vol.45 (10), p.1714-1716

2024

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Mechanism study of Hot Carrier Degradation Recovery by Gate Induced Drain Leakage in 14nm n FinFET

IEEE electron device letters, 2024-09, p.1-1

2024

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A 200-Gb/s PAM-4 Transmitter with 1.6-Vppd Output Swing and Clock Skew Correction in 12-nm FinFET

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2

2024

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Algorithmically-Enhanced Design of Spintronic-Based Tunable True Random Number Generator for Dependable Stochastic Computing

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-08, p.1-1

2024

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A comprehensive investigation of total ionizing dose effects on bulk FinFETs through TCAD simulation

Microelectronics and reliability, 2024-12, Vol.163, p.115534, Article 115534

2024

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Nano-Meter Resolution Line-Offset Detector Arrays (LODAs) for Pattern Monitoring in EUV Lithography System

IEEE transactions on electron devices, 2024-11, Vol.71 (11), p.6850-6856

2024

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On the Output Conductance Dispersion due to Traps and Self-Heating in Large Bulk, FDSOI and FinFET nMOS Devices

2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 2024, p.345-348

2024

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In-MRAM Computing Based on Complementary-Sensing Time-Based Readout Circuit Using Hybrid VGSOT-MTJ/GAA-CNTFET

IEEE transactions on circuits and systems. II, Express briefs, 2024-09, p.1-1

2024

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Full 3-D Monte Carlo Simulation of Coupled Electron-Phonon Transport: Self-Heating in a Nanoscale FinFET

IEEE transactions on nanotechnology, 2024, Vol.23, p.696-703

2024

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Modeling of HCI effect in nFinFET for circuit reliability simulation

Microelectronics and reliability, 2024-12, Vol.163, p.115543, Article 115543

2024

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An Integer-Floating-Point Dual-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Chips

IEEE journal of solid-state circuits, 2024-10, p.1-13

2024

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Channel Trimming Process to Improve Electro-Thermal Characteristics for Sub-3-nm Node Si Nanosheet FETs

IEEE transactions on electron devices, 2024-11, Vol.71 (11), p.7184-7191

2024

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The Reliability and Noise Investigation of Boron Diffusion Under Positive Bias Temperature Instability in 16 nm Node High Voltage FinFETs

3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM With Leakage Saving Circuits in 3-nm FinFET for HPC Applications

High-Temperature Retention Stability of Multibit Ferroelectric HfZrO₂ FinFET With SiGe/Si Superlattice Channel for Enhanced Speed and Memory Window

Optimization of Multi-fins FinFET Implemented on SOI Wafer Based on SiGe and Gaussian Process Regression

Improved Electrical Characteristics of Ge FinFET CMOS by Plasma-Enhanced Oxidation and Partial Nitridation with Supercritical Fluid Treatment

A 4-mW 2.2-6.9 GHz LNA in 16 nm FinFET Technology for Cryogenic Applications

Understanding the Self-Heating Effects Measured With the AC Output Conductance Method in Advanced FinFET Nodes

Self-Heating Effect Analysis and Characterization of 6T SRAM Based on Delay Variation

Cryogenic Temperature Effects on 16nm FinFet Performance and Mismatch

Synthesizable 10-bit Stochastic TDC Using Common-Mode Time Dithering and Passive Approximate Adder with 0.012mm2 Active Area in 12nm FinFET

CAPE: Criticality-Aware Performance and Energy Optimization Policy for NCFET-Based Caches

Elevated-Epi (Elepi) Technique for 3D IC With Stacked FinFETs, Interlevel Metal, and 25 \times 33 mm ^} Single-Crystalline Silicon on SiO \text

Millimeter-Wave CMOS Devices Design With Mobility Enhancement and Parasitic RC Suppression for Super-350 GHz \textit} and \textit} in Multiring nMOSFETs

Analyzing the Influence of Source/Drain Growth Height and Lateral Growth Depth in FinFETs Through XGBoost and SHAP

Mechanism study of Hot Carrier Degradation Recovery by Gate Induced Drain Leakage in 14nm n FinFET

A 200-Gb/s PAM-4 Transmitter with 1.6-Vppd Output Swing and Clock Skew Correction in 12-nm FinFET

Algorithmically-Enhanced Design of Spintronic-Based Tunable True Random Number Generator for Dependable Stochastic Computing

A comprehensive investigation of total ionizing dose effects on bulk FinFETs through TCAD simulation

Nano-Meter Resolution Line-Offset Detector Arrays (LODAs) for Pattern Monitoring in EUV Lithography System

On the Output Conductance Dispersion due to Traps and Self-Heating in Large Bulk, FDSOI and FinFET nMOS Devices

In-MRAM Computing Based on Complementary-Sensing Time-Based Readout Circuit Using Hybrid VGSOT-MTJ/GAA-CNTFET

Full 3-D Monte Carlo Simulation of Coupled Electron-Phonon Transport: Self-Heating in a Nanoscale FinFET

Modeling of HCI effect in nFinFET for circuit reliability simulation

An Integer-Floating-Point Dual-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Chips

Channel Trimming Process to Improve Electro-Thermal Characteristics for Sub-3-nm Node Si Nanosheet FETs

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