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High-k/Metal-Gate Fully Depleted SOI CMOS With Single-Silicide Schottky Source/Drain With Sub-30-nm Gate Length

IEEE electron device letters, 2010-04, Vol.31 (4), p.275-277

2010

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High- \kappa/Metal-Gate Fully Depleted SOI CMOS With Single-Silicide Schottky Source/Drain With Sub-30-nm Gate Length

IEEE electron device letters, 2010-04, Vol.31 (4), p.275-277

2010

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Simulation Study of Reduced Self-Heating in Novel Thin-SOI Vertical Bipolar Transistors

2005 International Conference On Simulation of Semiconductor Processes and Devices, 2005, p.55-58

2005

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High speed lateral trench detectors with a junction substrate

61st Device Research Conference. Conference Digest (Cat. No.03TH8663), 2003, p.73-74

2003

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A novel Si/SiGe heterojunction pMOSFET with reduced short-channel effects and enhanced drive current

IEEE transactions on electron devices, 2000-10, Vol.47 (10), p.1943-1949

2000

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Investigation of CMOS devices with embedded SiGe source/drain on hybrid orientation substrates

Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005, 2005, p.28-29

2005

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Simulation Analysis of Series Resistance for SOI MOSFET in Nanometer Regime

2005 International Conference On Simulation of Semiconductor Processes and Devices, 2005, p.239-242

2005

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Improved hot-carrier and short-channel performance in vertical nMOSFETs with graded channel doping

IEEE transactions on electron devices, 2002-11, Vol.49 (11), p.1962-1968

2002

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High-[Formula Omitted]/Metal-Gate Fully Depleted SOI CMOS With Single-Silicide Schottky Source/Drain With Sub-30-nm Gate Length

IEEE electron device letters, 2010-04, Vol.31 (4), p.275

2010

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Systematic Characterization of Pseudomorphic (110) Intrinsic SiGe Epitaxial Films for Hybrid Orientation Technology with Embedded SiGe Source/Drain

MRS proceedings, 2006, Vol.913, Article 0913-D01-02

2006

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Vertical SiGe-base bipolar transistors on CMOS-compatible SOI substrate

2003 Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting (IEEE Cat. No.03CH37440), 2003, p.215-218

2003

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Vertical p -type high-mobility heterojunction metal–oxide–semiconductor field-effect transistors

Applied physics letters, 2001-05, Vol.78 (21), p.3334-3336

2001

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SiGe heterojunction vertical p -type metal–oxide–semiconductor field-effect transistors with Si cap

Applied physics letters, 2000-09, Vol.77 (11), p.1656-1658

2000

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Asymmetric Si/Si sub(1-x)Ge sub(x) channel vertical p-type metal-oxide-semiconductor field-effect transistor

Solid-state electronics, 2001-02, Vol.45 (2), p.281-285

2001

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An asymmetric Si/Si 1− xGe x channel vertical p-type metal-oxide-semiconductor field-effect transistor

Solid-state electronics, 2001, Vol.45 (2), p.281-285

2001

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An asymmetric Si/Si1−xGex channel vertical p-type metal-oxide-semiconductor field-effect transistor

Solid-state electronics, 2001-02, Vol.45 (2), p.281-285

2001

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A simulation study on thin SOI bipolar transistors with fully or partially depleted collector

Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, 2002, p.28-31

2002

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Physical model enhancement and exploration of bandgap engineering in novel sub-100nm pMOSFETs

Ouyang, Qiqing Christine

2000

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A comprehensive simulation study of strained-Si/SiGe nMODFET scaling for RF applications

International Conference on Simulation of Semiconductor Processes and Devices, 2002, p.59-62

2002

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FDSOI CMOS with dual backgate control for performance and power modulation

2009 International Symposium on VLSI Technology, Systems, and Applications, 2009, p.84-85

2009

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Characteristics of high performance PFETs with embedded SiGe source/drain and channels on 45/spl deg/ rotated wafers

IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech), 2005, p.27-28

2005

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Si/sub 1-x/Gex channel vertical PMOSFET with asymmetric Ge profile

Device Research Conference. Conference Digest (Cat. No.01TH8561), 2001, p.30-31

2001

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Collaborative Innovation Centers (CICs): Toward Smart Service System Design

Serviceology for Smart Service System, p.385-391

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Quantum effects along the channel of ultra-scaled Si-based MOSFETs?

International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138), 2000, p.291-294

2000

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Fabrication of a novel vertical pMOSFET with enhanced drive current and reduced short-channel effects and floating body effects

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184), 2001, p.53-54

2001

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High-k/Metal-Gate Fully Depleted SOI CMOS With Single-Silicide Schottky Source/Drain With Sub-30-nm Gate Length

High- \kappa/Metal-Gate Fully Depleted SOI CMOS With Single-Silicide Schottky Source/Drain With Sub-30-nm Gate Length

Simulation Study of Reduced Self-Heating in Novel Thin-SOI Vertical Bipolar Transistors

High speed lateral trench detectors with a junction substrate

A novel Si/SiGe heterojunction pMOSFET with reduced short-channel effects and enhanced drive current

Investigation of CMOS devices with embedded SiGe source/drain on hybrid orientation substrates

Simulation Analysis of Series Resistance for SOI MOSFET in Nanometer Regime

Improved hot-carrier and short-channel performance in vertical nMOSFETs with graded channel doping

High-[Formula Omitted]/Metal-Gate Fully Depleted SOI CMOS With Single-Silicide Schottky Source/Drain With Sub-30-nm Gate Length

Systematic Characterization of Pseudomorphic (110) Intrinsic SiGe Epitaxial Films for Hybrid Orientation Technology with Embedded SiGe Source/Drain

Vertical SiGe-base bipolar transistors on CMOS-compatible SOI substrate

Vertical p -type high-mobility heterojunction metal–oxide–semiconductor field-effect transistors

SiGe heterojunction vertical p -type metal–oxide–semiconductor field-effect transistors with Si cap

Asymmetric Si/Si sub(1-x)Ge sub(x) channel vertical p-type metal-oxide-semiconductor field-effect transistor

An asymmetric Si/Si 1− xGe x channel vertical p-type metal-oxide-semiconductor field-effect transistor

An asymmetric Si/Si1−xGex channel vertical p-type metal-oxide-semiconductor field-effect transistor

A simulation study on thin SOI bipolar transistors with fully or partially depleted collector

Physical model enhancement and exploration of bandgap engineering in novel sub-100nm pMOSFETs

A comprehensive simulation study of strained-Si/SiGe nMODFET scaling for RF applications

FDSOI CMOS with dual backgate control for performance and power modulation

Characteristics of high performance PFETs with embedded SiGe source/drain and channels on 45/spl deg/ rotated wafers

Si/sub 1-x/Gex channel vertical PMOSFET with asymmetric Ge profile

Collaborative Innovation Centers (CICs): Toward Smart Service System Design

Quantum effects along the channel of ultra-scaled Si-based MOSFETs?

Fabrication of a novel vertical pMOSFET with enhanced drive current and reduced short-channel effects and floating body effects

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