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Comparative study of sensitive volume and triggering criteria of SEB in 600 V planar and trench IGBTs

Microelectronics and reliability, 2011-09, Vol.51 (9-11), p.1990-1994

2011

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MOS-IGBT power devices for high-temperature operation in smart power SOI technology

Microelectronics and reliability, 2011-09, Vol.51 (9-11), p.1980-1984

2011

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Reliability of ESD protection devices designed in a 3D technology

Microelectronics and reliability, 2014-09, Vol.54 (9-10), p.2272-2277

2014

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Autonomous power supply for aeronautical health monitoring sensors

Journal of physics. Conference series, 2018-07, Vol.1052 (1), p.12031

2018

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Self-Powered energy harvester strain sensing device for structural health monitoring

Journal of physics. Conference series, 2016-11, Vol.773 (1), p.12070

2016

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On-chip measurement to analyze failure mechanisms of ICs under system level ESD stress

Microelectronics and reliability, 2013-09, Vol.53 (9-11), p.1278-1283

2013

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Building-up of system level ESD modeling: Impact of a decoupling capacitance on ESD propagation

Microelectronics and reliability, 2013-02, Vol.53 (2), p.221-228

2013

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Powering a Commercial Datalogger by Energy Harvesting from Generated Aeroacoustic Noise

Journal of physics. Conference series, 2014-01, Vol.557 (1), p.12025-5

2014

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Under Voltage Lock-Out Design Rules for Proper Start-Up of Energy Autonomous Systems Powered by Supercapacitors

Journal of physics. Conference series, 2013-12, Vol.476 (1), p.12121-5

2013

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SEB Characterization of Commercial Power MOSFETs With Backside Laser and Heavy Ions of Different Ranges

IEEE transactions on nuclear science, 2008-08, Vol.55 (4), p.2166-2173

2008

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IEEE_Xplore

ESD failure signature in capacitive RF MEMS switches

Microelectronics and reliability, 2008-08, Vol.48 (8), p.1237-1240

2008

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Evaluation of the ESD performance of local protections based on SCR or bi-SCR with dynamic or static trigger circuit in 32 nm

Microelectronics and reliability, 2010-09, Vol.50 (9), p.1379-1382

2010

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Failure mechanisms of discrete protection device subjected to repetitive electrostatic discharges (ESD)

Microelectronics and reliability, 2009-09, Vol.49 (9), p.1103-1106

2009

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Transient voltage overshoots of high voltage ESD protections based on bipolar transistors in smart power technology

2010 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 2010, p.253-256

2010

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IEEE_Xplore

Latch-up ring design guidelines to improve electrostatic discharge (ESD) protection scheme efficiency

IEEE journal of solid-state circuits, 2004-10, Vol.39 (10), p.1778-1782

2004

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IEEE_Xplore

Prediction of LIN communication robustness against EFT events using dedicated failure models

Microelectronics and reliability, 2017-09, Vol.76-77, p.685-691

2017

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Analysis and compact modeling of a vertical grounded-base n-p-n bipolar transistor used as ESD protection in a smart power technology

IEEE journal of solid-state circuits, 2001-09, Vol.36 (9), p.1373-1381

2001

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IEEE_Xplore

20GHz on-chip measurement of ESD waveform for system level analysis

Microelectronics and reliability, 2015-11, Vol.55 (11), p.2276-2283

2015

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Impact of non-linear capacitances on transient waveforms during system level ESD stress

Microelectronics and reliability, 2016-09, Vol.64, p.88-92

2016

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Optimization of a MOS–IGBT–SCR ESD protection component in smart power SOI technology

Microelectronics and reliability, 2015-08, Vol.55 (9-10), p.1476-1480

2015

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Sensitive Volume and Triggering Criteria of SEB in Classic Planar VDMOS

IEEE transactions on nuclear science, 2010-08, Vol.57 (4), p.1900-1907

2010

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IEEE_Xplore

Identification of the physical signatures of CDM induced latent defects into a DC–DC converter using low frequency noise measurements

Microelectronics and reliability, 2007-09, Vol.47 (9), p.1456-1461

2007

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Long-term reliability of silicon bipolar transistors subjected to low constraints

Microelectronics and reliability, 2007-09, Vol.47 (9), p.1590-1594

2007

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Study of the ESD defects impact on ICs reliability

Microelectronics and reliability, 2004-09, Vol.44 (9), p.1811-1815

2004

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A System-Level Electrostatic-Discharge-Protection Modeling Methodology for Time-Domain Analysis

IEEE transactions on electromagnetic compatibility, 2013-02, Vol.55 (1), p.45-57

2013

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IEEE_Xplore

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Comparative study of sensitive volume and triggering criteria of SEB in 600 V planar and trench IGBTs

MOS-IGBT power devices for high-temperature operation in smart power SOI technology

Reliability of ESD protection devices designed in a 3D technology

Autonomous power supply for aeronautical health monitoring sensors

Self-Powered energy harvester strain sensing device for structural health monitoring

On-chip measurement to analyze failure mechanisms of ICs under system level ESD stress

Building-up of system level ESD modeling: Impact of a decoupling capacitance on ESD propagation

Powering a Commercial Datalogger by Energy Harvesting from Generated Aeroacoustic Noise

Under Voltage Lock-Out Design Rules for Proper Start-Up of Energy Autonomous Systems Powered by Supercapacitors

SEB Characterization of Commercial Power MOSFETs With Backside Laser and Heavy Ions of Different Ranges

ESD failure signature in capacitive RF MEMS switches

Evaluation of the ESD performance of local protections based on SCR or bi-SCR with dynamic or static trigger circuit in 32 nm

Failure mechanisms of discrete protection device subjected to repetitive electrostatic discharges (ESD)

Transient voltage overshoots of high voltage ESD protections based on bipolar transistors in smart power technology

Latch-up ring design guidelines to improve electrostatic discharge (ESD) protection scheme efficiency

Prediction of LIN communication robustness against EFT events using dedicated failure models

Analysis and compact modeling of a vertical grounded-base n-p-n bipolar transistor used as ESD protection in a smart power technology

20GHz on-chip measurement of ESD waveform for system level analysis

Impact of non-linear capacitances on transient waveforms during system level ESD stress

Optimization of a MOS–IGBT–SCR ESD protection component in smart power SOI technology

Sensitive Volume and Triggering Criteria of SEB in Classic Planar VDMOS

Identification of the physical signatures of CDM induced latent defects into a DC–DC converter using low frequency noise measurements

Long-term reliability of silicon bipolar transistors subjected to low constraints

Study of the ESD defects impact on ICs reliability

A System-Level Electrostatic-Discharge-Protection Modeling Methodology for Time-Domain Analysis

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