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Mouse Models as Tools to Explore Cytidine-to-Uridine RNA Editing

Methods in Enzymology, 2007, Vol.424, p.417-435

2007

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Hierarchical data organization for effective retrieval of similar shaders

Proceedings of the 2012 ACM Research in Applied Computation Symposium, 2012, p.43-48

2012

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Peripheral vision function training contents for people with low vision with Python tkinter

2022 13th International Conference on Information and Communication Technology Convergence (ICTC), 2022, p.739-741

2022

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A functional design for smart glasses for low vision people that provides visual assistance based on various image processing technologies

2022 International Conference on Electronics, Information, and Communication (ICEIC), 2022, p.1-3

2022

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A/C Load Forecasting Using Deep Learning

2017 International Conference on Computational Science and Computational Intelligence (CSCI), 2017, p.1840-1841

2017

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A Classification method of Fake News based on Ensemble Learning

Proceedings of the 2020 ACM International Conference on Intelligent Computing and its Emerging Applications, 2020, p.1-4

2020

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Characterization of APOBEC3G, a homolog of APOBEC1 involved in antiretroviral defense

Cho, Soo-Jin

2008

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“Road to Damascus” for piano and orchestra

Cho, Soo Jin

2008

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Effects of interventions to enhance social interactions between preschool children with special needs and their peers: A meta-analysis

Cho, Soo Jin

2004

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Prediction of 4-year risk for coronary artery calcification using ensemble-based classification

2013 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2013, Vol.2013, p.3210-3213

2013

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Optimal shape coding under buffer constraints

Proceedings 1998 International Conference on Image Processing. ICIP98 (Cat. No.98CB36269), 1998, Vol.1, p.290-294 vol.1

1998

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Applicable design of multi-functional cascade heat pump system for an office building

E3S Web of Conferences, 2022, Vol.356, p.1033

2022

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25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications

2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, Vol.64, p.350-352

2021

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Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory

2009 Symposium on VLSI Technology, 2009, p.192-193

2009

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A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.204-206

2018

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A numerical model and validation of phase change material integrated thermoelectric radiant cooling panel

E3S Web of Conferences, 2019, Vol.111, p.1001

2019

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A 16Gb/s/pin 8Gb GDDR6 DRAM with bandwidth extension techniques for high-speed applications

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.210-212

2018

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An LPDDR-based CXL-PNM Platform for TCO-efficient Inference of Transformer-based Large Language Models

2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2024, p.970-982

2024

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A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.206-208

2018

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23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power

2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019, p.378-380

2019

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A sub 1V CMOS bandgap reference with two diodes

MATEC Web of Conferences, 2016, Vol.54, p.12004

2016

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A 1.05A/m Minimum Magnetic Field Strength Single-Chip Fully Integrated Biometric Smart Card SoC Achieving 1014.7ms Transaction Time with Anti-Spoofing Fingerprint Authentication

2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, Vol.65, p.504-506

2022

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13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.234-236

2024

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Highly reliable vertical NAND technology with biconcave shaped storage layer and leakage controllable offset structure

2010 Symposium on VLSI Technology, 2010, p.173-174

2010

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Mouse Models as Tools to Explore Cytidine-to-Uridine RNA Editing

Hierarchical data organization for effective retrieval of similar shaders

Peripheral vision function training contents for people with low vision with Python tkinter

A functional design for smart glasses for low vision people that provides visual assistance based on various image processing technologies

A/C Load Forecasting Using Deep Learning

A Classification method of Fake News based on Ensemble Learning

Characterization of APOBEC3G, a homolog of APOBEC1 involved in antiretroviral defense

“Road to Damascus” for piano and orchestra

Effects of interventions to enhance social interactions between preschool children with special needs and their peers: A meta-analysis

Prediction of 4-year risk for coronary artery calcification using ensemble-based classification

Optimal shape coding under buffer constraints

Applicable design of multi-functional cascade heat pump system for an office building

25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications

Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory

A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking

A numerical model and validation of phase change material integrated thermoelectric radiant cooling panel

A 16Gb/s/pin 8Gb GDDR6 DRAM with bandwidth extension techniques for high-speed applications

An LPDDR-based CXL-PNM Platform for TCO-efficient Inference of Transformer-based Large Language Models

A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process

23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power

A sub 1V CMOS bandgap reference with two diodes

A 1.05A/m Minimum Magnetic Field Strength Single-Chip Fully Integrated Biometric Smart Card SoC Achieving 1014.7ms Transaction Time with Anti-Spoofing Fingerprint Authentication

The Clinical Outcomes of Lenalidomide and Dexamethasone in Patients with Relapsed/Refractory Multiple Myeloma: A Nationwide Registry Study of the Korean Multiple Myeloma Working Party (KMMWP)

13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process

Highly reliable vertical NAND technology with biconcave shaped storage layer and leakage controllable offset structure

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