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The science of plant‐based foods: Constructing next‐generation meat, fish, milk, and egg analogs

Comprehensive reviews in food science and food safety, 2021-07, Vol.20 (4), p.4049-4100

2021

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Erratum: “A Search for Analogs of KIC 8462852 (Boyajian’s Star): A Proof of Concept and the First Candidates” (2019, ApJL, 880, L7)

Astrophysical journal. Letters, 2020-09, Vol.900 (2), p.L46

Schmidt, Edward G.

2020

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Data Conversion Handbook

Kester, Walt

1, 2004

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A Time-Interleaved Digital-to-Analog Converter up to 118 GS/s With Integrated Analog Multiplexer in 28-nm FD-SOI CMOS Technology

IEEE journal of solid-state circuits, 2024-03, Vol.59 (3), p.1-15

2024

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Mixed-ADC/DAC Multipair Massive MIMO Relaying Systems: Performance Analysis and Power Optimization

IEEE transactions on communications, 2019-01, Vol.67 (1), p.140-153

2019

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A 28-nm 6-GHz 2-bit Continuous-Time ΔΣ ADC With −101-dBc THD and 120-MHz Bandwidth Using Blind Digital DAC Error Correction

IEEE journal of solid-state circuits, 2022-12, Vol.57 (12), p.3768-3780

2022

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Fully Synthesizable Low-Area Analogue-to-Digital Converters with Minimal Design Effort Based on the Dyadic Digital Pulse Modulation

IEEE access, 2020-01, Vol.8, p.1-1

2020

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A 12.5-MHz Bandwidth 77-dB SNDR SAR-Assisted Noise Shaping Pipeline ADC

IEEE journal of solid-state circuits, 2020-02, Vol.55 (2), p.312-321

2020

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A 243-mW 1.25-56-Gb/s Continuous Range PAM-4 42.5-dB IL ADC/DAC-Based Transceiver in 7-nm FinFET

IEEE journal of solid-state circuits, 2020-01, Vol.55 (1), p.6-18

2020

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Analog and Hybrid Computer Programming

Ulmann, Bernd

Second edition., 2023

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Understanding Delta-Sigma Data Converters

Second Edition., 2017

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An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch

IEEE journal of solid-state circuits, 2021-08, Vol.56 (8), p.2347-2359

2021

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A 9.1-ENOB 6-mW 10-Bit 500-MS/s Pipelined-SAR ADC With Current-Mode Residue Processing in 28-nm CMOS

IEEE journal of solid-state circuits, 2019-09, Vol.54 (9), p.2532-2542

2019

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A High Area-Efficiency 14-bit SAR ADC With Hybrid Capacitor DAC for Array Sensors

IEEE transactions on circuits and systems. I, Regular papers, 2020-12, Vol.67 (12), p.4396-4408

2020

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A Monolithically Integrated Large-Scale Optical Phased Array in Silicon-on-Insulator CMOS

IEEE journal of solid-state circuits, 2018-01, Vol.53 (1), p.275-296

2018

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Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques

IEEE transactions on circuits and systems. I, Regular papers, 2022-06, Vol.69 (6), p.2249-2262

2022

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A 0.4-V 13-bit 270-kS/s SAR-ISDM ADC With Opamp-Less Time-Domain Integrator

IEEE journal of solid-state circuits, 2019-06, Vol.54 (6), p.1648-1656

2019

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A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS

IEEE journal of solid-state circuits, 2020-06, Vol.55 (6), p.1553-1564

2020

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RxNN: A Framework for Evaluating Deep Neural Networks on Resistive Crossbars

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-02, Vol.40 (2), p.326-338

2021

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A 12-Bit, 300-MS/s Single-Channel Pipelined-SAR ADC With an Open-Loop MDAC

IEEE journal of solid-state circuits, 2019-05, Vol.54 (5), p.1446-1454

2019

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1-bit Massive MU-MIMO Precoding in VLSI

IEEE journal on emerging and selected topics in circuits and systems, 2017-12, Vol.7 (4), p.508-522

2017

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All-Digital High Resolution D/A Conversion by Dyadic Digital Pulse Modulation

IEEE transactions on circuits and systems. I, Regular papers, 2017-03, Vol.64 (3), p.573-584

Crovetti, Paolo S.

2017

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A Compact 10-b SAR ADC With Unit-Length Capacitors and a Passive FIR Filter

IEEE journal of solid-state circuits, 2019-03, Vol.54 (3), p.636-645

Harpe, Pieter

2019

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A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS

IEEE journal of solid-state circuits, 2018-12, Vol.53 (12), p.3672-3687

2018

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A Foreground Calibration for M-Channel Time-Interleaved Analog-to-Digital Converters Based on Genetic Algorithm

IEEE transactions on circuits and systems. I, Regular papers, 2021-04, Vol.68 (4), p.1444-1457

2021

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The science of plant‐based foods: Constructing next‐generation meat, fish, milk, and egg analogs

Erratum: “A Search for Analogs of KIC 8462852 (Boyajian’s Star): A Proof of Concept and the First Candidates” (2019, ApJL, 880, L7)

Data Conversion Handbook

A Time-Interleaved Digital-to-Analog Converter up to 118 GS/s With Integrated Analog Multiplexer in 28-nm FD-SOI CMOS Technology

Mixed-ADC/DAC Multipair Massive MIMO Relaying Systems: Performance Analysis and Power Optimization

A 28-nm 6-GHz 2-bit Continuous-Time ΔΣ ADC With −101-dBc THD and 120-MHz Bandwidth Using Blind Digital DAC Error Correction

Fully Synthesizable Low-Area Analogue-to-Digital Converters with Minimal Design Effort Based on the Dyadic Digital Pulse Modulation

A 12.5-MHz Bandwidth 77-dB SNDR SAR-Assisted Noise Shaping Pipeline ADC

A 243-mW 1.25-56-Gb/s Continuous Range PAM-4 42.5-dB IL ADC/DAC-Based Transceiver in 7-nm FinFET

Analog and Hybrid Computer Programming

Understanding Delta-Sigma Data Converters

An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch

A 9.1-ENOB 6-mW 10-Bit 500-MS/s Pipelined-SAR ADC With Current-Mode Residue Processing in 28-nm CMOS

A High Area-Efficiency 14-bit SAR ADC With Hybrid Capacitor DAC for Array Sensors

A Monolithically Integrated Large-Scale Optical Phased Array in Silicon-on-Insulator CMOS

Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques

A 0.4-V 13-bit 270-kS/s SAR-ISDM ADC With Opamp-Less Time-Domain Integrator

A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS

RxNN: A Framework for Evaluating Deep Neural Networks on Resistive Crossbars

A 12-Bit, 300-MS/s Single-Channel Pipelined-SAR ADC With an Open-Loop MDAC

1-bit Massive MU-MIMO Precoding in VLSI

All-Digital High Resolution D/A Conversion by Dyadic Digital Pulse Modulation

A Compact 10-b SAR ADC With Unit-Length Capacitors and a Passive FIR Filter

A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS

A Foreground Calibration for M-Channel Time-Interleaved Analog-to-Digital Converters Based on Genetic Algorithm

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