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High-performance Recessed-channel Reconfigurable Field-effect Transistor using Si-Ge Heterojunction

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2018, 18(3), 81, pp.392-395

2018

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Practical Silicon-Surface-Protection Method using Metal Layer

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2016, 16(4), 70, pp.470-480

2016

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MATLAB/Simulink Pulse-echo Ultrasound System Simulator with Electrical Impedance Matching

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2018, 18(3), 81, pp.328-336

2018

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Enabling Energy Efficient Image Encryption using Approximate Memoization

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2017, 17(3), 75, pp.465-472

2017

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Variation-tolerant Non-volatile Ternary Content Addressable Memory with Magnetic Tunnel Junction

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2017, 17(3), 75, pp.458-464

2017

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Accelerating Distance Transform Image based Hand Detection using CPU-GPU Heterogeneous Computing

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2016, 16(5), 71, pp.557-563

2016

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Current-Steered Active Balun with Phase Correction

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2015, 15(6), 66, pp.629-633

2015

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Novel Pass-transistor Logic based Ultralow Power Variation Resilient CMOS Full Adder

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2017, 17(2), 74, pp.302-317

2017

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Optimizing Fsync Performance with Dynamic Queue Depth Adaptation

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2015, 15(5), 65, pp.570-576

2015

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K-Nearest Neighbor Associative Memory with Reconfigurable Word-Parallel Architecture

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2016, 16(4), 70, pp.405-414

2016

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Highly Scalable NAND Flash Memory Cell Design Embracing Backside Charge Storage

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2015, 15(2), 62, pp.286-291

2015

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Wide-Input Range Dual Mode PWM / Linear Buck Converter with High robustness ESD Protection Circuit

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2015, 15(2), 62, pp.292-300

2015

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High Frame Rate VGA CMOS Image Sensor using Three Step Single Slope Column-Parallel ADCs

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2015, 15(1), 61, pp.22-28

2015

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High Throughput Radix-4 SISO Decoding Architecture with Reduced Memory Requirement

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2014, 14(4), 58, pp.407-418

2014

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Low-Complexity Triple-Error-Correcting Parallel BCH Decoder

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2013, 13(5), 53, pp.465-472

2013

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Low Phase Noise LC-VCO with Active Source Degeneration

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2013, 13(3), 51, pp.207-212

2013

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Full CMOS Single Supply PLC SoC ASIC with Integrated Analog Front-End

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2009, 9(2), , pp.85-90

2009

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High-performance Recessed-channel Reconfigurable Field-effect Transistor using Si-Ge Heterojunction

Practical Silicon-Surface-Protection Method using Metal Layer

MATLAB/Simulink Pulse-echo Ultrasound System Simulator with Electrical Impedance Matching

Enabling Energy Efficient Image Encryption using Approximate Memoization

Variation-tolerant Non-volatile Ternary Content Addressable Memory with Magnetic Tunnel Junction

Accelerating Distance Transform Image based Hand Detection using CPU-GPU Heterogeneous Computing

Current-Steered Active Balun with Phase Correction

Novel Pass-transistor Logic based Ultralow Power Variation Resilient CMOS Full Adder

Optimizing Fsync Performance with Dynamic Queue Depth Adaptation

K-Nearest Neighbor Associative Memory with Reconfigurable Word-Parallel Architecture

Highly Scalable NAND Flash Memory Cell Design Embracing Backside Charge Storage

Wide-Input Range Dual Mode PWM / Linear Buck Converter with High robustness ESD Protection Circuit

High Frame Rate VGA CMOS Image Sensor using Three Step Single Slope Column-Parallel ADCs

High Throughput Radix-4 SISO Decoding Architecture with Reduced Memory Requirement

Low-Complexity Triple-Error-Correcting Parallel BCH Decoder

Low Phase Noise LC-VCO with Active Source Degeneration

Full CMOS Single Supply PLC SoC ASIC with Integrated Analog Front-End

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