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Epidermal thymic stromal lymphopoietin predicts the development of atopic dermatitis during infancy

Journal of allergy and clinical immunology, 2016-04, Vol.137 (4), p.1282-1285.e4

2016

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Adaptive Digital Background Gain Mismatch Calibration for Multi-lane High-speed Serial Links

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2015, 15(1), 61, pp.96-100

2015

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Temperature‐Adaptive Back‐Bias Voltage Generator for an RCAT Pseudo SRAM

ETRI Journal, 2010, 32(3), , pp.406-413

2010

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A 6 Gbps/pin Low‐Power Half‐Duplex Active Cross‐Coupled LVDS Transceiver with Switched Termination

ETRI Journal, 2008, 30(4), , pp.612-614

2008

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High-Speed Low-Power Global On-Chip Interconnect Based on Delayed Symbol Transmission

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2012, 12(2), 46, pp.168-174

2012

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Temperature-Adaptive Back-Bias Voltage Generator for an RCAT Pseudo SRAM

ETRI journal, 2010-06, Vol.32 (3), p.406-413

2010

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Blind-oversampling adaptive oversample-level DFE receiver for unsynchronized global on-chip serial links

IEICE Electronics Express, 2013-01, Vol.10 (9), p.20120830-20120830

2013

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A 6 Gbps/pin Low-Power Half-Duplex Active Cross-Coupled LVDS Transceiver with Switched Termination

ETRI journal, 2008-02, Vol.30 (4), p.612-614

2008

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An all-digital PLL with supply insensitive digitally controlled oscillator

IEICE Electronics Express, 2013-01, Vol.10 (5), p.20120902-20120902

2013

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A fully digital clock and data recovery with fast frequency offset acquisition technique for MIPI LLI applications

IEICE Electronics Express, 2013-01, Vol.10 (10), p.20130178-20130178

2013

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Adaptive Digital Background Gain Mismatch Calibration for Multi-lane High-speed Serial Links

Journal of semiconductor technology and science, 2015, Vol.15 (1), p.96-100

2015

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Virtual fine delay line using one-stage inverter delay

Electronics letters, 2003-01, Vol.39 (2), p.189-190

2003

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CMOS cross-coupled charge pump with improved latch-up immunity

IEICE Electronics Express, 2009-01, Vol.6 (11), p.736-742

2009

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New low-voltage small-area mixed-voltage I/O buffer

IEICE Electronics Express, 2009, Vol.6 (13), p.897-903

2009

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Column redundancy scheme for multiple I/O DRAM using mapping table

Electronics letters, 2000-05, Vol.36 (11), p.940-942, Article 940

2000

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Food Allergy Management in Elementary, Middle and High Schools of Korea (P04-058-19)

Current developments in nutrition, 2019-06, Vol.3 (Suppl 1), p.nzz051.P04-058-19, Article nzz051.P04-058-19

2019

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A 5-Gbit/s CDR circuit with 1.4 mW multi-PFD phase rotating PLL

IEICE Electronics Express, 2014, Vol.11 (24), p.20140828-20140828

2014

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High-Speed Low-Power Global On-Chip Interconnect Based on Delayed Symbol Transmission

Journal of semiconductor technology and science, 2012, Vol.12 (2), p.168-174

2012

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A pre-emphasis output buffer control scheme for a GDDR3 SDRAM interface

IEICE Electronics Express, 2008-01, Vol.5 (12), p.446-450

2008

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Asymptomatic lymphangioma involving the spleen and retroperitoneum in adults

World journal of gastroenterology : WJG, 2009-11, Vol.15 (44), p.5620-5623

2009

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High Speed Pulse-based Flip-Flop with Pseudo MUX-type Scan for Standard Cell Library

Journal of semiconductor technology and science, 2006, Vol.6 (2), p.74-78

2006

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Diagnostic delay in inflammatory bowel disease increases the risk of intestinal surgery

World journal of gastroenterology : WJG, 2017-09, Vol.23 (35), p.6474-6481

2017

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Power-efficient low-voltage bootstrapped CMOS latcheddriver

Electronics letters, 1999-11, Vol.35 (24), p.2113-2115

1999

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Design of an Image Interpolator for Low Computation Complexity

Journal of Information Processing Systems, 2006-12, Vol.2 (3), p.153-158

2006

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Column redundancy scheme for multipleI/O DRAM using mapping table

Electronics letters, 2000-05, Vol.36 (11), p.940-942

2000

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Epidermal thymic stromal lymphopoietin predicts the development of atopic dermatitis during infancy

Adaptive Digital Background Gain Mismatch Calibration for Multi-lane High-speed Serial Links

Temperature‐Adaptive Back‐Bias Voltage Generator for an RCAT Pseudo SRAM

A 6 Gbps/pin Low‐Power Half‐Duplex Active Cross‐Coupled LVDS Transceiver with Switched Termination

High-Speed Low-Power Global On-Chip Interconnect Based on Delayed Symbol Transmission

Temperature-Adaptive Back-Bias Voltage Generator for an RCAT Pseudo SRAM

Blind-oversampling adaptive oversample-level DFE receiver for unsynchronized global on-chip serial links

A 6 Gbps/pin Low-Power Half-Duplex Active Cross-Coupled LVDS Transceiver with Switched Termination

An all-digital PLL with supply insensitive digitally controlled oscillator

A fully digital clock and data recovery with fast frequency offset acquisition technique for MIPI LLI applications

Adaptive Digital Background Gain Mismatch Calibration for Multi-lane High-speed Serial Links

Virtual fine delay line using one-stage inverter delay

CMOS cross-coupled charge pump with improved latch-up immunity

New low-voltage small-area mixed-voltage I/O buffer

Column redundancy scheme for multiple I/O DRAM using mapping table

Food Allergy Management in Elementary, Middle and High Schools of Korea (P04-058-19)

A 5-Gbit/s CDR circuit with 1.4 mW multi-PFD phase rotating PLL

High-Speed Low-Power Global On-Chip Interconnect Based on Delayed Symbol Transmission

A pre-emphasis output buffer control scheme for a GDDR3 SDRAM interface

Asymptomatic lymphangioma involving the spleen and retroperitoneum in adults

High Speed Pulse-based Flip-Flop with Pseudo MUX-type Scan for Standard Cell Library

Diagnostic delay in inflammatory bowel disease increases the risk of intestinal surgery

Power-efficient low-voltage bootstrapped CMOS latcheddriver

Design of an Image Interpolator for Low Computation Complexity

Column redundancy scheme for multipleI/O DRAM using mapping table

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