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Epidermal thymic stromal lymphopoietin predicts the development of atopic dermatitis during infancy

Journal of allergy and clinical immunology, 2016-04, Vol.137 (4), p.1282-1285.e4

2016

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P‐200: N‐type Host Derived from Phenyl‐Triazine Moiety for Low Driving Voltage in Blue Phosphorescent Organic Light‐Emitting Diodes

SID International Symposium Digest of technical papers, 2024-06, Vol.55 (1), p.2147-2149

2024

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A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking

IEEE journal of solid-state circuits, 2012, Vol.47 (1), p.107-116

2012

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A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW

2011 IEEE International Solid-State Circuits Conference, 2011, p.500-502

2011

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Antiadipogenic Effect of Korean Glasswort (Salicornia herbacea L.) Water Extract on 3T3-L1 Adipocytes

Han'guk Sikp'um Yŏngyang Kwahakhoe chi, 2014-06, Vol.43 (6), p.814-821

2014

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A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 \times 128 I/Os Using TSV Based Stacking

IEEE journal of solid-state circuits, 2012-01, Vol.47 (1), p.107-116

2012

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A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology

2012 IEEE International Solid-State Circuits Conference, 2012, p.430-432

2012

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10.4 A 5.8Gb/s adaptive integrating duobinary-based DFE receiver for multi-drop memory interface

2015 IEEE International Solid State Circuits Conference (ISSCC), 2015, p.1-3

2015

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Temperature-Adaptive Back-Bias Voltage Generator for an RCAT Pseudo SRAM

ETRI journal, 2010-06, Vol.32 (3), p.406-413

2010

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CMOS charge pump with separated charge sharing for improved boosting ratio and relaxed timing restriction

2011 9th IEEE International Conference on ASIC, 2011, p.133-136

2011

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A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW

2011 IEEE International Solid-State Circuits Conference, 2011, p.498-500

2011

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A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008, p.278-613

2008

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A 6 Gbps/pin Low-Power Half-Duplex Active Cross-Coupled LVDS Transceiver with Switched Termination

ETRI journal, 2008-02, Vol.30 (4), p.612-614

2008

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A new approach of NAND flash cell trap analysis using RTN characteristics

2011 Symposium on VLSI Technology - Digest of Technical Papers, 2011, p.206-207

2011

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A new GIDL phenomenon by field effect of neighboring cell transistors and its control solutions in sub-30 nm NAND flash devices

2012 Symposium on VLSI Technology (VLSIT), 2012, p.23-24

2012

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A 6Gb/s/pin pseudo-differential signaling using common-mode noise rejection techniques without reference signal for DRAM interfaces

2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009, p.138-139,139a

2009

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A highly reliable multi-cell antifuse scheme using DRAM cell capacitors

2010 Proceedings of ESSCIRC, 2010, p.482-485

2010

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Adaptive Digital Background Gain Mismatch Calibration for Multi-lane High-speed Serial Links

Journal of semiconductor technology and science, 2015, Vol.15 (1), p.96-100

2015

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Conditional-capture flip-flop technique for statistical power reduction

2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056), 2000, p.290-291

2000

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A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction

2010 IEEE International Solid-State Circuits Conference - (ISSCC), 2010, p.434-435

2010

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A 100nm Double-Stacked 500MHz 72Mb Separate-I/O Synchronous SRAM with Automatic Cell-Bias Scheme and Adaptive Block Redundancy

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008, p.386-622

2008

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Wafer-Level Characterization of Probecards using NAC Probing

2008 IEEE International Test Conference, 2008, p.1-9

2008

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Novel Low-Voltage Small-Area I/O Buffer for Mixed-Voltage Application

Control and Automation, and Energy System Engineering, 2011, Vol.256, p.364-370

2011

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An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007, p.492-617

2007

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Food Allergy Management in Elementary, Middle and High Schools of Korea (P04-058-19)

Current developments in nutrition, 2019-06, Vol.3 (Suppl 1), p.nzz051.P04-058-19, Article nzz051.P04-058-19

2019

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Epidermal thymic stromal lymphopoietin predicts the development of atopic dermatitis during infancy

P‐200: N‐type Host Derived from Phenyl‐Triazine Moiety for Low Driving Voltage in Blue Phosphorescent Organic Light‐Emitting Diodes

A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking

A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW

Antiadipogenic Effect of Korean Glasswort (Salicornia herbacea L.) Water Extract on 3T3-L1 Adipocytes

A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 \times 128 I/Os Using TSV Based Stacking

A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology

10.4 A 5.8Gb/s adaptive integrating duobinary-based DFE receiver for multi-drop memory interface

Temperature-Adaptive Back-Bias Voltage Generator for an RCAT Pseudo SRAM

CMOS charge pump with separated charge sharing for improved boosting ratio and relaxed timing restriction

A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW

A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques

A 6 Gbps/pin Low-Power Half-Duplex Active Cross-Coupled LVDS Transceiver with Switched Termination

A new approach of NAND flash cell trap analysis using RTN characteristics

A new GIDL phenomenon by field effect of neighboring cell transistors and its control solutions in sub-30 nm NAND flash devices

A 6Gb/s/pin pseudo-differential signaling using common-mode noise rejection techniques without reference signal for DRAM interfaces

A highly reliable multi-cell antifuse scheme using DRAM cell capacitors

Adaptive Digital Background Gain Mismatch Calibration for Multi-lane High-speed Serial Links

Conditional-capture flip-flop technique for statistical power reduction

A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction

A 100nm Double-Stacked 500MHz 72Mb Separate-I/O Synchronous SRAM with Automatic Cell-Bias Scheme and Adaptive Block Redundancy

Wafer-Level Characterization of Probecards using NAC Probing

Novel Low-Voltage Small-Area I/O Buffer for Mixed-Voltage Application

An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion

Food Allergy Management in Elementary, Middle and High Schools of Korea (P04-058-19)

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