UB Paderborn / Katalog / Suche / in CDI

1 – 25 von 41

Sortiert nach

Gate-based high fidelity spin readout in a CMOS device

Nature nanotechnology, 2019-08, Vol.14 (8), p.737-741

2019

Volltextzugriff (PDF)

Low-temperature electrical characterization of junctionless transistors

Solid-state electronics, 2013-02, Vol.80, p.135-141

2013

Volltextzugriff (PDF)

Less mobility degradation induced by transverse electric-field in junctionless transistors

Applied physics letters, 2014-11, Vol.105 (21)

2014

Volltextzugriff (PDF)

Low-temperature operation of junctionless nanowire transistors: Less surface roughness scattering effects and dominant scattering mechanisms

Applied physics letters, 2014-12, Vol.105 (26)

2014

Volltextzugriff (PDF)

Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width

IEEE transactions on electron devices, 2013-02, Vol.60 (2), p.727-732

2013

Volltextzugriff (PDF)

Low-frequency noise behavior of junctionless transistors compared to inversion-mode transistors

Solid-state electronics, 2013-03, Vol.81, p.101-104

2013

Volltextzugriff (PDF)

Effects of channel width variation on electrical characteristics of tri-gate Junctionless transistors

Solid-state electronics, 2013-03, Vol.81, p.58-62

2013

Volltextzugriff (PDF)

Separation of surface accumulation and bulk neutral channel in junctionless transistors

Applied physics letters, 2014-06, Vol.104 (26)

2014

Volltextzugriff (PDF)

Development of a CMOS Route for Electron Pumps to Be Used in Quantum Metrology

Technologies (Basel), 2016-03, Vol.4 (1), p.10

2016

Volltextzugriff (PDF)

Channel-Width-Dependent Mobility Degradation in Bulk Conduction Regime of Tri-Gate Junctionless Transistors

IEEE transactions on electron devices, 2022-06, Vol.69 (6), p.3037-3041

2022

Volltextzugriff (PDF)

Impact of Channel Length on the Operation of Junctionless Transistors With Substrate Biasing

IEEE transactions on electron devices, 2021-06, Vol.68 (6), p.3070-3073

2021

Volltextzugriff (PDF)

Channel width dependent subthreshold operation of tri-gate junctionless transistors

Solid-state electronics, 2020-09, Vol.171, p.107860, Article 107860

2020

Volltextzugriff (PDF)

Controlling the Effective Channel Thickness of Junctionless Transistors by Substrate Bias

IEEE transactions on electron devices, 2020-11, Vol.67 (11), p.4736-4740

2020

Volltextzugriff (PDF)

Impact of Hot Carrier Aging on the Performance of Triple-Gate Junctionless MOSFETs

IEEE transactions on electron devices, 2020-02, Vol.67 (2), p.424-429

2020

Volltextzugriff (PDF)

Impact of (Quasi-)Ballistic Transport on Operation of Complementary Metal--Oxide--Semiconductor Inverters Based on Fully-Depleted Silicon-on-Insulator and Nanowire Devices

Japanese Journal of Applied Physics, 2011-01, Vol.50 (1), p.014103-014103-7

2011

Volltextzugriff (PDF)

Analytical Drain Current Compact Model in the Depletion Operation Region of Short-Channel Triple-Gate Junctionless Transistors

IEEE transactions on electron devices, 2017-01, Vol.64 (1), p.66-72

2017

Volltextzugriff (PDF)

Impact of series resistance on the operation of junctionless transistors

Solid-state electronics, 2017-03, Vol.129, p.103-107

2017

Volltextzugriff (PDF)

Effect of Temperature on the Performance of Triple-Gate Junctionless Transistors

IEEE transactions on electron devices, 2018-08, Vol.65 (8), p.3562-3566

2018

Volltextzugriff (PDF)

A New Method for Series Resistance Extraction of Nanometer MOSFETs

IEEE transactions on electron devices, 2017-07, Vol.64 (7), p.2797-2803

2017

Volltextzugriff (PDF)

Back-gate effects and mobility characterization in junctionless transistor

Solid-state electronics, 2016-11, Vol.125, p.154-160

2016

Volltextzugriff (PDF)

Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs

Solid-state electronics, 2018-11, Vol.149, p.62-70

2018

Volltextzugriff (PDF)

A Simple Method for Estimation of Silicon Film Thickness in Tri-Gate Junctionless Transistors

IEEE electron device letters, 2018-09, Vol.39 (9), p.1282-1285

2018

Volltextzugriff (PDF)

Electrical characterization of vertically stacked p-FET SOI nanowires

Solid-state electronics, 2018-03, Vol.141, p.84-91

2018

Volltextzugriff (PDF)

Series resistance in different operation regime of junctionless transistors

Solid-state electronics, 2018-03, Vol.141, p.92-95

2018

Volltextzugriff (PDF)

Behavior of subthreshold conduction in junctionless transistors

Solid-state electronics, 2016-10, Vol.124, p.58-63

2016

Volltextzugriff (PDF)

1 – 25 von 41

Suche als RSS-Feed

Aktive Filter

Zeitschrift / SerieMicroelectronic Engineering

ThemaMicroelectronics

Suchergebnisse filtern

Filter anzeigen

Nur zeigen

Geprüft (Peer-Review)
(32)
Mit Volltextzugriff
(36)

Publikationsform

Sprache

Englisch
(41)
Japanisch
(8)

Erscheinungsjahr

n.n

Thema

Engineering Sciences
(39)
Micro And Nanotechnologies
(39)
Science & Technology
(35)
Technology
(31)
Engineering
(29)
Physical Sciences
(29)
Physics
(29)
Engineering, Electrical & Electronic
(28)
Physics, Applied
(26)
Transistors
(21)
Logic Gates
(12)
Physics, Condensed Matter
(12)
Electronics
(11)
Junctionless Transistors
(11)
Semiconductor Devices
(11)
Silicon
(10)
Degradation
(8)
Threshold Voltage
(8)
Applied Sciences
(7)

14 weitere anzeigen...

Weniger anzeigen...

Menü

Weitere Dienste

Einstellungen

Gate-based high fidelity spin readout in a CMOS device

Low-temperature electrical characterization of junctionless transistors

Less mobility degradation induced by transverse electric-field in junctionless transistors

Low-temperature operation of junctionless nanowire transistors: Less surface roughness scattering effects and dominant scattering mechanisms

Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width

Low-frequency noise behavior of junctionless transistors compared to inversion-mode transistors

Effects of channel width variation on electrical characteristics of tri-gate Junctionless transistors

Separation of surface accumulation and bulk neutral channel in junctionless transistors

Development of a CMOS Route for Electron Pumps to Be Used in Quantum Metrology

Channel-Width-Dependent Mobility Degradation in Bulk Conduction Regime of Tri-Gate Junctionless Transistors

Impact of Channel Length on the Operation of Junctionless Transistors With Substrate Biasing

Channel width dependent subthreshold operation of tri-gate junctionless transistors

Controlling the Effective Channel Thickness of Junctionless Transistors by Substrate Bias

Impact of Hot Carrier Aging on the Performance of Triple-Gate Junctionless MOSFETs

Impact of (Quasi-)Ballistic Transport on Operation of Complementary Metal--Oxide--Semiconductor Inverters Based on Fully-Depleted Silicon-on-Insulator and Nanowire Devices

Analytical Drain Current Compact Model in the Depletion Operation Region of Short-Channel Triple-Gate Junctionless Transistors

Impact of series resistance on the operation of junctionless transistors

Effect of Temperature on the Performance of Triple-Gate Junctionless Transistors

A New Method for Series Resistance Extraction of Nanometer MOSFETs

Back-gate effects and mobility characterization in junctionless transistor

Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs

A Simple Method for Estimation of Silicon Film Thickness in Tri-Gate Junctionless Transistors

Electrical characterization of vertically stacked p-FET SOI nanowires

Series resistance in different operation regime of junctionless transistors

Behavior of subthreshold conduction in junctionless transistors

Aktive Filter

Suchergebnisse filtern