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Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques

2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA), 2020, p.638-651

2020

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New Attacks and Defense for Encrypted-Address Cache

2019 ACM/IEEE 46th Annual International Symposium on Computer Architecture (ISCA), 2019, p.360-371

Qureshi, Moinuddin K.

2019

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An experimental study of data retention behavior in modern DRAM devices: implications for retention time profiling mechanisms

Proceedings of the 40th Annual International Symposium on computer architecture, 2013, p.60-71

2013

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QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips

2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA), 2021, p.944-957

2021

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MuonTrap: Preventing Cross-Domain Spectre-Like Attacks by Capturing Speculative State

2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA), 2020, p.132-144

2020

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A new stochastic computing multiplier with application to deep convolutional neural networks

2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC), 2017, p.1-6

2017

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TWiCe: Preventing Row-hammering by Exploiting Time Window Counters

2019 ACM/IEEE 46th Annual International Symposium on Computer Architecture (ISCA), 2019, p.385-396

2019

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The reach profiler (REAPER): Enabling the mitigation of DRAM retention failures via profiling at aggressive conditions

2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA), 2017, p.255-268

2017

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ArchShield: architectural framework for assisting DRAM scaling by tolerating high error rates

Proceedings of the 40th Annual International Symposium on computer architecture, 2013, p.72-83

2013

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A 29.12 TOPS/W and 1.13 TOPS/mm2 NAS-Optimized Mixed-Precision DNN Accelerator with Vector Split- and-Combination Systolic in 28nm CMOS

2024 IEEE Custom Integrated Circuits Conference (CICC), 2024, p.1-2

2024

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CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off

2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA), 2020, p.666-679

2020

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Random Fill Cache Architecture

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014, p.203-215

2014

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Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology

2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2017, p.273-287

2017

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Widely Tunable 4th Order Switched Gm-C Band-Pass Filter Based on N-Path Filters

IEEE journal of solid-state circuits, 2012, Vol.47 (12), p.3105-3119

2012

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Security analysis of integrated circuit camouflaging

Proceedings of the 2013 ACM SIGSAC conference on computer & communications security, 2013, p.709-720

2013

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Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks

2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2016, p.1-6

2016

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A 6-bit 10-GS/s 17.6-mW CMOS ADC with 0.8-V supply

2023 IEEE Custom Integrated Circuits Conference (CICC), 2023, p.1-2

2023

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Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems

Proceedings of the 40th Annual International Symposium on computer architecture, 2013, p.48-59

2013

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Bouquet of Instruction Pointers: Instruction Pointer Classifier-based Spatial Hardware Prefetching

2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA), 2020, p.118-131

2020

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A 112 Gb/s -8.2 dBm Sensitivity 4-PAM Linear TIA in 16nm CMOS with Co-Packaged Photodiodes

2022 IEEE Custom Integrated Circuits Conference (CICC), 2022, p.1-2

2022

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Perceptron-Based Prefetch Filtering

2019 ACM/IEEE 46th Annual International Symposium on Computer Architecture (ISCA), 2019, p.1-13

2019

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Equivalence among stochastic logic circuits and its application

2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2015, p.1-6

2015

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34.4 A Cryogenic Controller IC for Superconducting Qubits with DRAG Pulse Generation by Direct Synthesis without Using Memory

2023 IEEE International Solid- State Circuits Conference (ISSCC), 2023, p.33-35

2023

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Die Stacking (3D) Microarchitecture

2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06), 2006, p.469-479

2006

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Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches

2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06), 2006, p.423-432

2006

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IEEE_Xplore

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Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques

New Attacks and Defense for Encrypted-Address Cache

An experimental study of data retention behavior in modern DRAM devices: implications for retention time profiling mechanisms

QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips

MuonTrap: Preventing Cross-Domain Spectre-Like Attacks by Capturing Speculative State

A new stochastic computing multiplier with application to deep convolutional neural networks

TWiCe: Preventing Row-hammering by Exploiting Time Window Counters

The reach profiler (REAPER): Enabling the mitigation of DRAM retention failures via profiling at aggressive conditions

ArchShield: architectural framework for assisting DRAM scaling by tolerating high error rates

A 29.12 TOPS/W and 1.13 TOPS/mm2 NAS-Optimized Mixed-Precision DNN Accelerator with Vector Split- and-Combination Systolic in 28nm CMOS

CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off

Random Fill Cache Architecture

Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology

Widely Tunable 4th Order Switched Gm-C Band-Pass Filter Based on N-Path Filters

Security analysis of integrated circuit camouflaging

Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks

A 6-bit 10-GS/s 17.6-mW CMOS ADC with 0.8-V supply

Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems

Bouquet of Instruction Pointers: Instruction Pointer Classifier-based Spatial Hardware Prefetching

A 112 Gb/s -8.2 dBm Sensitivity 4-PAM Linear TIA in 16nm CMOS with Co-Packaged Photodiodes

Perceptron-Based Prefetch Filtering

Equivalence among stochastic logic circuits and its application

34.4 A Cryogenic Controller IC for Superconducting Qubits with DRAG Pulse Generation by Direct Synthesis without Using Memory

Die Stacking (3D) Microarchitecture

Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches

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