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Maximizing Yield per Area of Highly Parallel CMPs Using Hardware Redundancy
IEEE transactions on computer-aided design of integrated circuits and systems, 2014-10, Vol.33 (10), p.1545-1558
2014
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DS-LFSR: a BIST TPG for low switching activity
IEEE transactions on computer-aided design of integrated circuits and systems, 2002-07, Vol.21 (7), p.842-851
2002
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An automatic test pattern generator for minimizing switching activity during scan testing activity
IEEE transactions on computer-aided design of integrated circuits and systems, 2002-08, Vol.21 (8), p.954-968
2002
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LT-RTPG: a new test-per-scan BIST TPG for low switching activity
IEEE transactions on computer-aided design of integrated circuits and systems, 2006-08, Vol.25 (8), p.1565-1574
2006
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Threshold Testing: Improving Yield for Nanoscale VLSI
IEEE transactions on computer-aided design of integrated circuits and systems, 2009-12, Vol.28 (12), p.1883-1895
2009
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Design of efficient BIST test pattern generators for delay testing
IEEE transactions on computer-aided design of integrated circuits and systems, 1996-12, Vol.15 (12), p.1568-1575
1996
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Analytical models for crosstalk excitation and propagation in VLSI circuits
IEEE transactions on computer-aided design of integrated circuits and systems, 2002-10, Vol.21 (10), p.1117-1131
2002
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Efficient BIST TPG design and test set compaction via input reduction
IEEE transactions on computer-aided design of integrated circuits and systems, 1998-08, Vol.17 (8), p.692-705
1998
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Path delay fault diagnosis in combinational circuits with implicit fault enumeration
IEEE transactions on computer-aided design of integrated circuits and systems, 2001-10, Vol.20 (10), p.1226-1235, Article 1226
2001
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Test embedding with discrete logarithms
IEEE transactions on computer-aided design of integrated circuits and systems, 1995-05, Vol.14 (5), p.554-566
1995
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