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AES Datapath Optimization Strategies for Low-Power Low-Energy Multisecurity-Level Internet-of-Things Applications

IEEE transactions on very large scale integration (VLSI) systems, 2017-12, Vol.25 (12), p.3281-3290

2017

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A Hardware Architecture of NIST Lightweight Cryptography applied in IPSec to Secure High-throughput Low-latency IoT Networks

IEEE access, 2023-01, Vol.11, p.1-1

2023

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An Adaptive Hardware Architecture using Quantized HOG Features for Object Detection

2022 International Conference on IC Design and Technology (ICICDT), 2022, p.113-116

2022

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An Efficient Hardware Implementation of Residual Data Binarization in HEVC CABAC Encoder

Electronics (Basel), 2020-04, Vol.9 (4), p.684

2020

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AXI-NoC: High-Performance Adaptation Unit for ARM Processors in Network-on-Chip Architectures

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2017-01, Vol.E100.A (8), p.1650-1660

2017

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Reducing Bitrate and Increasing the Quality of Inter Frame by Avoiding Quantization Errors in Stationary Blocks

EAI endorsed transactions on industrial networks and intelligent systems, 2020, Vol.7 (22), p.162795

2020

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A Novel Hardware Architecture for Human Detection using HOG-SVM Co-Optimization

2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2019, p.33-36

2019

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A Lightweight AEAD encryption core to secure IoT applications

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2020, p.35-38

2020

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Adaptive Architectures, Circuits and Technology Solutions for Future IoT Systems

Journal of low-power electronics, 2017-09, Vol.13 (3), p.298-309

2017

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An Efficient Hardware Implementation of Artificial Neural Network based on Stochastic Computing

2018 5th NAFOSTED Conference on Information and Computer Science (NICS), 2018, p.237-242

2018

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A Variable Precision Approach for Deep Neural Networks

2019 International Conference on Advanced Technologies for Communications (ATC), 2019, p.313-318

2019

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Fully Synthesizable Dynamic Voltage Comparator across technology nodes and scaled supply voltages

2024 IEEE International Symposium on Circuits and Systems (ISCAS), 2024, p.1-5

2024

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Ultra low-power and low-energy 32-bit datapath AES architecture for IoT applications

2016 International Conference on IC Design and Technology (ICICDT), 2016, p.1-4

2016

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Tiny Neuron Network System based on RISC-V Processor: A Decentralized Approach for IoT Applications

2022 International Conference on Advanced Technologies for Communications (ATC), 2022, p.98-103

2022

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A Low-Power CT Second-Order VCO-Based ΔΣADC for Audio Recording on Skywater 130-nm

2022 International Conference on Advanced Technologies for Communications (ATC), 2022, p.110-115

2022

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Novel PUF-Based Authentication Protocol for IoT Devices with Secure Boot and Fuzzy Matching

2023 International Conference on Advanced Technologies for Communications (ATC), 2023, p.78-83

2023

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FPGA-Based Human Detection System using HOG-SVM Algorithm

2023 International Conference on Advanced Technologies for Communications (ATC), 2023, p.72-77

2023

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A Highly Digital VCO-based ADC for IoT Applications on Skywater 130nm

2021 8th NAFOSTED Conference on Information and Computer Science (NICS), 2021, p.549-554

2021

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An Efficient Event-driven Neuromorphic Architecture for Deep Spiking Neural Networks

2019 32nd IEEE International System-on-Chip Conference (SOCC), 2019, p.144-149

2019

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Accurate and low complex cell histogram generation by bypass the gradient of pixel computation

2017 4th NAFOSTED Conference on Information and Computer Science, 2017, p.201-206

2017

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Efficient Binary Arithmetic Encoder for HEVC with multiple bypass bin processing

2017 7th International Conference on Integrated Circuits, Design, and Verification (ICDV), 2017, p.82-87

2017

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Reducing temporal redundancy in MJPEG using Zipfian estimation techniques

2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2014, p.65-68

2014

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H.264/AVC hardware encoders and low-power features

2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2014, p.77-80

2014

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Hardware implementation for entropy coding and byte stream packing engine in H.264/AVC

2013 International Conference on Advanced Technologies for Communications (ATC 2013), 2013, p.360-365

2013

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High-performance adaption of ARM processors into Network-on-Chip architectures

2013 IEEE International SOC Conference, 2013, p.222-227

2013

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AES Datapath Optimization Strategies for Low-Power Low-Energy Multisecurity-Level Internet-of-Things Applications

A Hardware Architecture of NIST Lightweight Cryptography applied in IPSec to Secure High-throughput Low-latency IoT Networks

An Adaptive Hardware Architecture using Quantized HOG Features for Object Detection

An Efficient Hardware Implementation of Residual Data Binarization in HEVC CABAC Encoder

AXI-NoC: High-Performance Adaptation Unit for ARM Processors in Network-on-Chip Architectures

Reducing Bitrate and Increasing the Quality of Inter Frame by Avoiding Quantization Errors in Stationary Blocks

A Novel Hardware Architecture for Human Detection using HOG-SVM Co-Optimization

A Lightweight AEAD encryption core to secure IoT applications

Adaptive Architectures, Circuits and Technology Solutions for Future IoT Systems

An Efficient Hardware Implementation of Artificial Neural Network based on Stochastic Computing

A Variable Precision Approach for Deep Neural Networks

Fully Synthesizable Dynamic Voltage Comparator across technology nodes and scaled supply voltages

Ultra low-power and low-energy 32-bit datapath AES architecture for IoT applications

Tiny Neuron Network System based on RISC-V Processor: A Decentralized Approach for IoT Applications

A Low-Power CT Second-Order VCO-Based ΔΣADC for Audio Recording on Skywater 130-nm

Novel PUF-Based Authentication Protocol for IoT Devices with Secure Boot and Fuzzy Matching

FPGA-Based Human Detection System using HOG-SVM Algorithm

A Highly Digital VCO-based ADC for IoT Applications on Skywater 130nm

An Efficient Event-driven Neuromorphic Architecture for Deep Spiking Neural Networks

Accurate and low complex cell histogram generation by bypass the gradient of pixel computation

Efficient Binary Arithmetic Encoder for HEVC with multiple bypass bin processing

Reducing temporal redundancy in MJPEG using Zipfian estimation techniques

H.264/AVC hardware encoders and low-power features

Hardware implementation for entropy coding and byte stream packing engine in H.264/AVC

High-performance adaption of ARM processors into Network-on-Chip architectures

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