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A 0.077 to 0.168 nJ/bit/iteration scalable 3GPP LTE turbo decoder with an adaptive sub-block parallel scheme and an embedded DVFS engine

IEEE Custom Integrated Circuits Conference 2010, 2010, p.1-4

2010

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IEEE_Xplore

A 0.1-micron gate Al(0.5)In(0.5)As/Ga(0.5)In(0.5)As MODFET fabricated on GaAs substrates

IEEE transactions on electron devices, 1988-07, Vol.35, p.818-823

1988

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0-1 Programming Problem Continuous Solution and Application to Topological Optimization of the Continuum Structure

Chen, Shi

2008

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0.1 /spl mu/m enhancement-mode pseudomorphic InGaAs/InAlAs/InP HEMT

Conference Proceedings. 2001 International Conference on Indium Phosphide and Related Materials. 13th IPRM (Cat. No.01CH37198), 2001, p.180-183

2001

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IEEE_Xplore

A 0.1 /spl mu/m W-band HEMT production process for high yield and high performance low noise and power MMICs

Proceedings of 1994 IEEE GaAs IC Symposium, 1994, p.325-328

1994

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IEEE_Xplore

A 0.10 /spl mu/m gate length CMOS technology with 30 /spl Aring/ gate dielectric for 1.0 V-1.5 V applications

International Electron Devices Meeting. IEDM Technical Digest, 1997, p.223-226

1997

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IEEE_Xplore

0.12-mu m gate III-V nitride HFET' s with high contact resistances

IEEE electron device letters, 1997-04, Vol.18 (4), p.141-143

1997

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0.12-μm gate III-V nitride HFET's with high contact resistances

IEEE electron device letters, 1997-04, Vol.18 (4), p.141-143

1997

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IEEE_Xplore

A 0.13 /spl mu/m CMOS platform with Cu/low-k interconnects for system on chip applications

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184), 2001, p.101-102

2001

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IEEE_Xplore

A 0.13 /spl mu/m logic-based embedded DRAM technology with electrical fuses, Cu interconnect in SiLK/sup TM/, sub-7 ns random access time and its extension to the 0.10 /spl mu/m generation

International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224), 2001, p.18.5.1-18.5.4

2001

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IEEE_Xplore

0.174 dB/km Hollow Core Double Nested Antiresonant Nodeless Fiber (DNANF)

2022 Optical Fiber Communications Conference and Exhibition (OFC), 2022, p.1-3

2022

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A 0.18 μm CMOS 10-Gb/S multichannel transmitter with duty-cycle correction

ASIC, 2003. Proceedings. 5th International Conference on, 2003, Vol.1, p.534-536 Vol.1

2003

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IEEE_Xplore

A 0.18 /spl mu/m BiCMOS technology featuring 120/100 GHz (f/sub T//f/sub max/) HBT and ASIC-compatible CMOS using copper interconnect

Proceedings of the 2001 BIPOLAR/BiCMOS Circuits and Technology Meeting (Cat. No.01CH37212), 2001, p.143-146

2001

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IEEE_Xplore

A 0.18 /spl mu/m high-performance logic technology

1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325), 1999, p.105-106

1999

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IEEE_Xplore

0.18 um modular triple self-aligned embedded split-gate flash memory

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104), 2000, p.120-121

2000

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IEEE_Xplore

A 0.18 μm CMOS on-chip skin detection scheme based on NPNP-triple-junction structure

2007 International Symposium on Integrated Circuits, 2007, p.333-336

2007

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IEEE_Xplore

A 0.18um Dual Gate (3.5nm/6.8nm) CMOS Technology with Copper Metallurgy for Logic, SRAM, and Analog Applications

29th European Solid-State Device Research Conference, 1999, Vol.1, p.632-635

1999

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IEEE_Xplore

0.18um Low-power Series EEPROM IP Sesign

Chen, Xin Rui

2006

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A 0.18μm CMOS fluorescent detector system for bio-sensing application

Journal of semiconductors, 2009 (1), p.44-49

刘楠陈国平洪志良

2009

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0.2％新洁尔灭和5％甲酚皂消毒液灭菌效果研究

食品安全质量检测学报, 2020, Vol.11 (23), p.8709-8714

2020

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0.23W隔离式数字芯片供电电源的分析与实现

电力电子技术, 2011, Vol.45 (5), p.69-71

周猛陈乾宏

2011

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A 0.25 /spl mu/m gate length CMOS technology for 1V low power applications-device design and power/performance considerations

1996 Symposium on VLSI Technology. Digest of Technical Papers, 1996, p.68-69

1996

Link zum Volltext
IEEE_Xplore

0.35% absolute efficiency gain of bifacial N-type Si solar cells by industrial Metal Wrap Through Technology

2012 38th IEEE Photovoltaic Specialists Conference, 2012, p.002289-002291

2012

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IEEE_Xplore

A 0.3GHz-3.3GHz highly linear CMOS LNA for multimode applications

2012 IEEE International Conference on Wireless Information Technology and Systems (ICWITS), 2012, p.1-4

2012

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IEEE_Xplore

0—4周龄京红蛋鸡饲粮蛋氨酸需要量研究

中国农业科学, 2014, Vol.47 (12), p.2446-2454

宋丹岳洪源陈秀丽李连彬高玉鹏武书庚

2014

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A 0.077 to 0.168 nJ/bit/iteration scalable 3GPP LTE turbo decoder with an adaptive sub-block parallel scheme and an embedded DVFS engine

A 0.1-micron gate Al(0.5)In(0.5)As/Ga(0.5)In(0.5)As MODFET fabricated on GaAs substrates

0-1 Programming Problem Continuous Solution and Application to Topological Optimization of the Continuum Structure

0.1 /spl mu/m enhancement-mode pseudomorphic InGaAs/InAlAs/InP HEMT

A 0.1 /spl mu/m W-band HEMT production process for high yield and high performance low noise and power MMICs

A 0.10 /spl mu/m gate length CMOS technology with 30 /spl Aring/ gate dielectric for 1.0 V-1.5 V applications

0.12-mu m gate III-V nitride HFET' s with high contact resistances

0.12-μm gate III-V nitride HFET's with high contact resistances

A 0.13 /spl mu/m CMOS platform with Cu/low-k interconnects for system on chip applications

A 0.13 /spl mu/m logic-based embedded DRAM technology with electrical fuses, Cu interconnect in SiLK/sup TM/, sub-7 ns random access time and its extension to the 0.10 /spl mu/m generation

0.174 dB/km Hollow Core Double Nested Antiresonant Nodeless Fiber (DNANF)

A 0.18 μm CMOS 10-Gb/S multichannel transmitter with duty-cycle correction

A 0.18 /spl mu/m BiCMOS technology featuring 120/100 GHz (f/sub T//f/sub max/) HBT and ASIC-compatible CMOS using copper interconnect

A 0.18 /spl mu/m high-performance logic technology

0.18 um modular triple self-aligned embedded split-gate flash memory

A 0.18 μm CMOS on-chip skin detection scheme based on NPNP-triple-junction structure

A 0.18um Dual Gate (3.5nm/6.8nm) CMOS Technology with Copper Metallurgy for Logic, SRAM, and Analog Applications

0.18um Low-power Series EEPROM IP Sesign

A 0.18μm CMOS fluorescent detector system for bio-sensing application

0.2％新洁尔灭和5％甲酚皂消毒液灭菌效果研究

0.23W隔离式数字芯片供电电源的分析与实现

A 0.25 /spl mu/m gate length CMOS technology for 1V low power applications-device design and power/performance considerations

0.35% absolute efficiency gain of bifacial N-type Si solar cells by industrial Metal Wrap Through Technology

A 0.3GHz-3.3GHz highly linear CMOS LNA for multimode applications

0—4周龄京红蛋鸡饲粮蛋氨酸需要量研究

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