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A Reference-Free Phase Noise Measurement Circuit Achieving 24.2-fs Periodic Jitter Sensitivity and 275-fsrms Resolution With Background Self-Calibration

IEEE journal of solid-state circuits, 2023-04, Vol.58 (4), p.993-1001

2023

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A 25 Gb/s 1.13 pJ/b −10.8 dBm Input Sensitivity Optical Receiver in 40 nm CMOS

IEEE journal of solid-state circuits, 2017-03, Vol.52 (3), p.747-756

2017

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An 80–84.8 GHz PLL with auto-tracking Miller divider for FMCW applications

Analog integrated circuits and signal processing, 2024-03, Vol.118 (3), p.523-537

2024

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Introduction to the Special Section on the 2020 Asian Solid-State Circuits Conference (A-SSCC)

IEEE journal of solid-state circuits, 2021-10, Vol.56 (10), p.2900-2901

2021

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A 25-Gb/s, 2.1-pJ/bit, Fully Integrated Optical Receiver With a Baud-Rate Clock and Data Recovery

IEEE journal of solid-state circuits, 2019-08, Vol.54 (8), p.2243-2254

2019

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A 103 fJ/b/dB, 10-26 Gb/s Receiver With a Dual Feedback Nested Loop CDR for Wide Bandwidth Jitter Tolerance Enhancement

IEEE journal of solid-state circuits, 2023-10, Vol.58 (10), p.1-11

2023

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A 50 Gb/s PAM-4 Transmitter With Feedforward Equalizer and Background Phase Error Calibration

IEEE transactions on circuits and systems. II, Express briefs, 2021-08, Vol.68 (8), p.2820-2824

2021

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Exploring Multiple Analog Placements With Partial-Monotonic Current Paths and Symmetry Constraints Using PCP-SP

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-12, Vol.39 (12), p.5056-5068

2020

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A 3.12 pJ/bit, 19-27 Gbps Receiver With 2-Tap DFE Embedded Clock and Data Recovery

IEEE journal of solid-state circuits, 2015-11, Vol.50 (11), p.2625-2634

2015

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Wide Tunning Range 60 GHz VCO and 40 GHz DCO Using Single Variable Inductor

IEEE transactions on circuits and systems. I, Regular papers, 2013-02, Vol.60 (2), p.257-267

2013

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A Monolithic Current-Mode Buck Converter With Advanced Control and Protection Circuits

IEEE transactions on power electronics, 2007-09, Vol.22 (5), p.1836-1846

2007

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A 10 GHz Dual-Loop PLL With Active Cycle-Jitter Correction Achieving 12dB Spur and 29% Jitter Reduction

IEEE open journal of circuits and systems, 2024, Vol.5, p.291-301

2024

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A 7.1 mW, 10 GHz All Digital Frequency Synthesizer With Dynamically Reconfigured Digital Loop Filter in 90 nm CMOS Technology

IEEE journal of solid-state circuits, 2010-03, Vol.45 (3), p.578-586

2010

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A 32 Gb/s PAM-4 Optical Transceiver With Active Back Termination in 40 nm CMOS Technology

IEEE open journal of circuits and systems, 2021, Vol.2, p.56-64

2021

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A Low-Jitter Cell-Based Digitally Controlled Oscillator With Differential Multiphase Outputs

IEEE transactions on very large scale integration (VLSI) systems, 2015-04, Vol.23 (4), p.766-770

2015

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Three-Dimensional Fully Symmetric Inductors, Transformer, and Balun in CMOS Technology

IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2007-07, Vol.54 (7), p.1413-1423

2007

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A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end

IEEE journal of solid-state circuits, 2005-06, Vol.40 (6), p.1388-1396

2005

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Distortion-characteristic estimation predistorter for high efficiency power amplifiers

IET signal processing, 2016-12, Vol.10 (9), p.1024-1030

2016

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A 3-10 GHz, 14 Bands CMOS Frequency Synthesizer With Spurs Reduction for MB-OFDM UWB System

IEEE transactions on very large scale integration (VLSI) systems, 2012-05, Vol.20 (5), p.948-958

2012

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A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter Suppression

IEEE transactions on circuits and systems. I, Regular papers, 2015-03, Vol.62 (3), p.743-751

2015

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A Single-Chip 2.5-Gb/s CMOS Burst-Mode Optical Receiver

IEEE transactions on circuits and systems. I, Regular papers, 2009-10, Vol.56 (10), p.2325-2331

2009

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A 20-Gb/s, 2.4 pJ/bit, Fully Integrated Optical Receiver with a Baud-Rate Clock and Data Recovery

2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, p.1-4

2018

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A 38/114 GHz Switched-Mode and Synchronous Lock Standing Wave Oscillator

IEEE microwave and wireless components letters, 2011-01, Vol.21 (1), p.40-42

2011

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A 160-GHz Frequency-Translation Phase-Locked Loop With RSSI Assisted Frequency Acquisition

IEEE transactions on circuits and systems. I, Regular papers, 2014-06, Vol.61 (6), p.1648-1655

2014

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Low-Power Programmable Pseudorandom Word Generator and Clock Multiplier Unit for High-Speed SerDes Applications

IEEE transactions on circuits and systems. I, Regular papers, 2008-07, Vol.55 (6), p.1495-1501

2008

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A Reference-Free Phase Noise Measurement Circuit Achieving 24.2-fs Periodic Jitter Sensitivity and 275-fsrms Resolution With Background Self-Calibration

A 25 Gb/s 1.13 pJ/b −10.8 dBm Input Sensitivity Optical Receiver in 40 nm CMOS

An 80–84.8 GHz PLL with auto-tracking Miller divider for FMCW applications

Introduction to the Special Section on the 2020 Asian Solid-State Circuits Conference (A-SSCC)

A 25-Gb/s, 2.1-pJ/bit, Fully Integrated Optical Receiver With a Baud-Rate Clock and Data Recovery

A 103 fJ/b/dB, 10-26 Gb/s Receiver With a Dual Feedback Nested Loop CDR for Wide Bandwidth Jitter Tolerance Enhancement

A 50 Gb/s PAM-4 Transmitter With Feedforward Equalizer and Background Phase Error Calibration

Exploring Multiple Analog Placements With Partial-Monotonic Current Paths and Symmetry Constraints Using PCP-SP

A 3.12 pJ/bit, 19-27 Gbps Receiver With 2-Tap DFE Embedded Clock and Data Recovery

Wide Tunning Range 60 GHz VCO and 40 GHz DCO Using Single Variable Inductor

A Monolithic Current-Mode Buck Converter With Advanced Control and Protection Circuits

A 10 GHz Dual-Loop PLL With Active Cycle-Jitter Correction Achieving 12dB Spur and 29% Jitter Reduction

A 7.1 mW, 10 GHz All Digital Frequency Synthesizer With Dynamically Reconfigured Digital Loop Filter in 90 nm CMOS Technology

A 32 Gb/s PAM-4 Optical Transceiver With Active Back Termination in 40 nm CMOS Technology

A Low-Jitter Cell-Based Digitally Controlled Oscillator With Differential Multiphase Outputs

Three-Dimensional Fully Symmetric Inductors, Transformer, and Balun in CMOS Technology

A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end

Distortion-characteristic estimation predistorter for high efficiency power amplifiers

A 3-10 GHz, 14 Bands CMOS Frequency Synthesizer With Spurs Reduction for MB-OFDM UWB System

A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter Suppression

A Single-Chip 2.5-Gb/s CMOS Burst-Mode Optical Receiver

A 20-Gb/s, 2.4 pJ/bit, Fully Integrated Optical Receiver with a Baud-Rate Clock and Data Recovery

A 38/114 GHz Switched-Mode and Synchronous Lock Standing Wave Oscillator

A 160-GHz Frequency-Translation Phase-Locked Loop With RSSI Assisted Frequency Acquisition

Low-Power Programmable Pseudorandom Word Generator and Clock Multiplier Unit for High-Speed SerDes Applications

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