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Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing

IEEE transactions on very large scale integration (VLSI) systems, 2010-08, Vol.18 (8), p.1225-1229

2010

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IEEE_Xplore

Design of Testable Reversible Sequential Circuits

IEEE transactions on very large scale integration (VLSI) systems, 2013-07, Vol.21 (7), p.1201-1209

2013

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IEEE_Xplore

Design of Logic Gates and Flip-Flops in High-Performance FinFET Technology

IEEE transactions on very large scale integration (VLSI) systems, 2013-11, Vol.21 (11), p.1975-1988

2013

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IEEE_Xplore

Electronics and Packaging Intended for Emerging Harsh Environment Applications: A Review

IEEE transactions on very large scale integration (VLSI) systems, 2018-10, Vol.26 (10), p.2085-2098

2018

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IEEE_Xplore

Low-Power and Area-Efficient Carry Select Adder

IEEE transactions on very large scale integration (VLSI) systems, 2012-02, Vol.20 (2), p.371-375

2012

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A Study of Tapered 3-D TSVs for Power and Thermal Integrity

IEEE transactions on very large scale integration (VLSI) systems, 2013-02, Vol.21 (2), p.306-319

2013

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IEEE_Xplore

ORION 2.0: A Power-Area Simulator for Interconnection Networks

IEEE transactions on very large scale integration (VLSI) systems, 2012-01, Vol.20 (1), p.191-196

2012

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IEEE_Xplore

Extracting secret keys from integrated circuits

IEEE transactions on very large scale integration (VLSI) systems, 2005-10, Vol.13 (10), p.1200-1205

2005

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IEEE_Xplore

A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits

IET computers & digital techniques, 2013-07, Vol.7 (4), p.167-181

2013

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Design of Ternary Logic Combinational Circuits Based on Quantum Dot Gate FETs

IEEE transactions on very large scale integration (VLSI) systems, 2013-05, Vol.21 (5), p.793-806

2013

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IEEE_Xplore

Resistive Switching: From Fundamentals of Nanoionic Redox Processes to Memristive Device Applications

1, 2016

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Memristor Bridge Synapse-Based Neural Network and Its Learning

IEEE transaction on neural networks and learning systems, 2012-09, Vol.23 (9), p.1426-1435

2012

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IEEE_Xplore

Scalable Packet Classification on FPGA

IEEE transactions on very large scale integration (VLSI) systems, 2012-09, Vol.20 (9), p.1668-1680

2012

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IEEE_Xplore

A Sensitivity Analysis of Power Signal Methods for Detecting Hardware Trojans Under Real Process and Environmental Conditions

IEEE transactions on very large scale integration (VLSI) systems, 2010-12, Vol.18 (12), p.1735-1744

2010

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IEEE_Xplore

Novel Architecture for Efficient FPGA Implementation of Elliptic Curve Cryptographic Processor Over GF(2163)

IEEE transactions on very large scale integration (VLSI) systems, 2013-12, Vol.21 (12), p.2330-2333

2013

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Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip

IEEE transactions on very large scale integration (VLSI) systems, 2013-10, Vol.21 (10), p.1823-1836

2013

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IEEE_Xplore

Attractivity Analysis of Memristor-Based Cellular Neural Networks With Time-Varying Delays

IEEE transaction on neural networks and learning systems, 2014-04, Vol.25 (4), p.704-717

2014

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IEEE_Xplore

Time-Domain CMOS Temperature Sensors With Dual Delay-Locked Loops for Microprocessor Thermal Monitoring

IEEE transactions on very large scale integration (VLSI) systems, 2012-09, Vol.20 (9), p.1590-1601

2012

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IEEE_Xplore

Design Exploration of Hybrid CMOS and Memristor Circuit by New Modified Nodal Analysis

IEEE transactions on very large scale integration (VLSI) systems, 2012-06, Vol.20 (6), p.1012-1025

2012

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IEEE_Xplore

Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design

IEEE transactions on very large scale integration (VLSI) systems, 2012-02, Vol.20 (2), p.319-332

2012

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IEEE_Xplore

A 1.2-V Piecewise Curvature-Corrected Bandgap Reference in 0.5 μm CMOS Process

IEEE transactions on very large scale integration (VLSI) systems, 2011-06, Vol.19 (6), p.1118-1122

2011

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HotSpot: a compact thermal modeling methodology for early-stage VLSI design

IEEE transactions on very large scale integration (VLSI) systems, 2006-05, Vol.14 (5), p.501-513

2006

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IEEE_Xplore

Low-Power Circuit Analysis and Design Based on Heterojunction Tunneling Transistors (HETTs)

IEEE transactions on very large scale integration (VLSI) systems, 2013-09, Vol.21 (9), p.1632-1643

2013

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IEEE_Xplore

Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I-Methodology and Design Strategies

IEEE transactions on very large scale integration (VLSI) systems, 2011-05, Vol.19 (5), p.725-736

2011

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IEEE_Xplore

Systematic Design of RSA Processors Based on High-Radix Montgomery Multipliers

IEEE transactions on very large scale integration (VLSI) systems, 2011-07, Vol.19 (7), p.1136-1146

2011

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IEEE_Xplore

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Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing

Design of Testable Reversible Sequential Circuits

Design of Logic Gates and Flip-Flops in High-Performance FinFET Technology

Electronics and Packaging Intended for Emerging Harsh Environment Applications: A Review

Low-Power and Area-Efficient Carry Select Adder

A Study of Tapered 3-D TSVs for Power and Thermal Integrity

ORION 2.0: A Power-Area Simulator for Interconnection Networks

Extracting secret keys from integrated circuits

A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits

Design of Ternary Logic Combinational Circuits Based on Quantum Dot Gate FETs

Resistive Switching: From Fundamentals of Nanoionic Redox Processes to Memristive Device Applications

Memristor Bridge Synapse-Based Neural Network and Its Learning

Scalable Packet Classification on FPGA

A Sensitivity Analysis of Power Signal Methods for Detecting Hardware Trojans Under Real Process and Environmental Conditions

Novel Architecture for Efficient FPGA Implementation of Elliptic Curve Cryptographic Processor Over GF(2163)

Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip

Attractivity Analysis of Memristor-Based Cellular Neural Networks With Time-Varying Delays

Time-Domain CMOS Temperature Sensors With Dual Delay-Locked Loops for Microprocessor Thermal Monitoring

Design Exploration of Hybrid CMOS and Memristor Circuit by New Modified Nodal Analysis

Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design

A 1.2-V Piecewise Curvature-Corrected Bandgap Reference in 0.5 μm CMOS Process

HotSpot: a compact thermal modeling methodology for early-stage VLSI design

Low-Power Circuit Analysis and Design Based on Heterojunction Tunneling Transistors (HETTs)

Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I-Methodology and Design Strategies

Systematic Design of RSA Processors Based on High-Radix Montgomery Multipliers

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