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A 0.0012 mm[sup.2] 6-bit 700 MS/s 1 mW Calibration-Free Pseudo-Loop-Unrolled SAR ADC in 28 nm CMOS

Electronics (Basel), 2022-06, Vol.11 (11)

2022

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A 0.0012 mm2 6-bit 700 MS/s 1 mW Calibration-Free Pseudo-Loop-Unrolled SAR ADC in 28 nm CMOS

Electronics (Basel), 2022-05, Vol.11 (11), p.1707

2022

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A 0.02 mm ^ 59.2 dB SFDR 4th-Order SC LPF With 0.5-to-10 MHz Bandwidth Scalability Exploiting a Recycling SC-Buffer Biquad

IEEE journal of solid-state circuits, 2015-09, Vol.50 (9), p.1988-2001

2015

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A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS

2011 IEEE International Solid-State Circuits Conference, 2011, p.188-190

2011

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A 0.0325-mm² 114-to-147-GHz 6-Bit Passive Vector-Modulated Phase Shifter With MN-Embedded Isolated Power Combiner Achieving

IEEE transactions on circuits and systems. I, Regular papers, 2023-01, Vol.70 (11), p.4394

2023

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A 0.0325-mm ^2 114-to-147-GHz 6-Bit Passive Vector-Modulated Phase Shifter With MN-Embedded Isolated Power Combiner Achieving 3.7 ^$ RMS Phase Error in 65-nm CMOS

IEEE transactions on circuits and systems. I, Regular papers, 2023-08, p.1-12

2023

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A 0.0325-mm² 114-to-147-GHz 6-Bit Passive Vector-Modulated Phase Shifter With MN-Embedded Isolated Power Combiner Achieving <3.7° RMS Phase Error in 65-nm CMOS

IEEE transactions on circuits and systems. I, Regular papers, 2023-11, Vol.70 (11), p.4394-4405

2023

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A 0.04 cc Power Amplifier Module with Fully Integrated Passives in a Hybrid LTCC Substrate for 5-GHz Wireless LANs

2002 32nd European Microwave Conference, 2002, p.1-4

2002

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A 0.055 mm2 Total Area Triple-Loop Wideband Fractional-N All-Digital Phase-Locked Loop Architecture for 1.9–6.1 GHz Frequency Tuning

Electronics (Basel), 2024-07, Vol.13 (13), p.2638

2024

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A 0.086-mm ^2 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28-nm CMOS

IEEE transactions on biomedical circuits and systems, 2019-02, Vol.13 (1), p.145-158

2019

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A 0.086-mm[Formula Omitted] 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28-nm CMOS

IEEE transactions on biomedical circuits and systems, 2019-01, Vol.13 (1), p.145

2019

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A 0.092-mm2 2-12-GHz Noise-Cancelling Low-Noise Amplifier With Gain Improvement and Noise Reduction

IEEE transactions on circuits and systems. II, Express briefs, 2022-10, Vol.69 (10), p.4013-4017

2022

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A 0.096-mm ^~1 -20-GHz Triple-Path Noise- Canceling Common-Gate Common-Source LNA With Dual Complementary pMOS-nMOS Configuration

IEEE transactions on microwave theory and techniques, 2020-01, Vol.68 (1), p.144-159

2020

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A 0.1-1.5 GHz multi-octave quadruple-stacked CMOS power amplifier

Journal of semiconductors, 2020-06, Vol.41 (6), p.62401-48

2020

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The 0-1 knapsack problem with fuzzy data

Fuzzy optimization and decision making, 2007-06, Vol.6 (2), p.163-172

2007

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0--1 Multiband Robust Optimization

Operations Research Proceedings 2013, 2014, p.89-95

2014

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0/1 Polytopes with Quadratic Chvátal Rank

Operations research, 2017-01, Vol.65 (1), p.212-220

2017

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0-1 Quadratic Knapsack Problems: An Exact Approach Based on a $t$-Linearization

SIAM journal on optimization, 2012-01, Vol.22 (4), p.1449-1468

2012

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A 0.13-µm implementation of 5 Gb/s and 3-mW folded parallel architecture for AES algorithm

International journal of electronics, 2014-02, Vol.101 (2), p.182-193

2014

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A 0.137 mm 2 9 GHz Hybrid Class-B/C QVCO With Output Buffering in 65 nm CMOS

IEEE microwave and wireless components letters, 2014-10, Vol.24 (10), p.716-718

2014

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A 0.137 mm ^} 9 GHz Hybrid Class-B/C QVCO With Output Buffering in 65 nm CMOS

IEEE microwave and wireless components letters, 2014-10, Vol.24 (10), p.716-718

2014

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A 0.14- }^ 1.4-mW 59.4-dB-SFDR 2.4-GHz ZigBee/WPAN Receiver Exploiting a "Split-LNTA + 50% LO" Topology in 65-nm CMOS

IEEE transactions on microwave theory and techniques, 2014-07, Vol.62 (7), p.1525-1534

2014

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A 0.14- hbox mm 2 1.4-mW 59.4-dB-SFDR 2.4-GHz ZigBee/WPAN Receiver Exploiting a "Split-LNTA + 50% LO" Topology in 65-nm CMOS

IEEE transactions on microwave theory and techniques, 2014-07, Vol.62 (7), p.1525-1534

2014

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A 0.14-mm2 1.4-mW 59.4-dB-SFDR 2.4-GHz ZigBee/WPAN Receiver Exploiting a Split-LNTA + 50% LO Topology in 65-nm CMOS

IEEE transactions on microwave theory and techniques, 2014, Vol.62 (7), p.1525-1534

2014

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A 0.15-to-0.5 V Body-Driven Dynamic Comparator with Rail-to-Rail ICMR

Journal of low power electronics and applications, 2023-06, Vol.13 (2), p.35

2023

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A 0.0012 mm[sup.2] 6-bit 700 MS/s 1 mW Calibration-Free Pseudo-Loop-Unrolled SAR ADC in 28 nm CMOS

A 0.0012 mm2 6-bit 700 MS/s 1 mW Calibration-Free Pseudo-Loop-Unrolled SAR ADC in 28 nm CMOS

A 0.02 mm ^ 59.2 dB SFDR 4th-Order SC LPF With 0.5-to-10 MHz Bandwidth Scalability Exploiting a Recycling SC-Buffer Biquad

A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS

A 0.0325-mm² 114-to-147-GHz 6-Bit Passive Vector-Modulated Phase Shifter With MN-Embedded Isolated Power Combiner Achieving

A 0.0325-mm ^2 114-to-147-GHz 6-Bit Passive Vector-Modulated Phase Shifter With MN-Embedded Isolated Power Combiner Achieving 3.7 ^$ RMS Phase Error in 65-nm CMOS

A 0.0325-mm² 114-to-147-GHz 6-Bit Passive Vector-Modulated Phase Shifter With MN-Embedded Isolated Power Combiner Achieving <3.7° RMS Phase Error in 65-nm CMOS

A 0.04 cc Power Amplifier Module with Fully Integrated Passives in a Hybrid LTCC Substrate for 5-GHz Wireless LANs

A 0.055 mm2 Total Area Triple-Loop Wideband Fractional-N All-Digital Phase-Locked Loop Architecture for 1.9–6.1 GHz Frequency Tuning

A 0.086-mm ^2 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28-nm CMOS

A 0.086-mm[Formula Omitted] 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28-nm CMOS

A 0.092-mm2 2-12-GHz Noise-Cancelling Low-Noise Amplifier With Gain Improvement and Noise Reduction

A 0.096-mm ^~1 -20-GHz Triple-Path Noise- Canceling Common-Gate Common-Source LNA With Dual Complementary pMOS-nMOS Configuration

A 0.1-1.5 GHz multi-octave quadruple-stacked CMOS power amplifier

The 0-1 knapsack problem with fuzzy data

0--1 Multiband Robust Optimization

0/1 Polytopes with Quadratic Chvátal Rank

0-1 Quadratic Knapsack Problems: An Exact Approach Based on a $t$-Linearization

A 0.13-µm implementation of 5 Gb/s and 3-mW folded parallel architecture for AES algorithm

A 0.137 mm 2 9 GHz Hybrid Class-B/C QVCO With Output Buffering in 65 nm CMOS

A 0.137 mm ^} 9 GHz Hybrid Class-B/C QVCO With Output Buffering in 65 nm CMOS

A 0.14- }^ 1.4-mW 59.4-dB-SFDR 2.4-GHz ZigBee/WPAN Receiver Exploiting a "Split-LNTA + 50% LO" Topology in 65-nm CMOS

A 0.14- hbox mm 2 1.4-mW 59.4-dB-SFDR 2.4-GHz ZigBee/WPAN Receiver Exploiting a "Split-LNTA + 50% LO" Topology in 65-nm CMOS

A 0.14-mm2 1.4-mW 59.4-dB-SFDR 2.4-GHz ZigBee/WPAN Receiver Exploiting a Split-LNTA + 50% LO Topology in 65-nm CMOS

A 0.15-to-0.5 V Body-Driven Dynamic Comparator with Rail-to-Rail ICMR

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