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An Implementation of Reconfigurable Match Table for FPGA-Based Programmable Switches

IEEE transactions on very large scale integration (VLSI) systems, 2024-11, Vol.32 (11), p.2121-2134

2024

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H3DAtten: Heterogeneous 3-D Integrated Hybrid Analog and Digital Compute-in-Memory Accelerator for Vision Transformer Self-Attention

IEEE transactions on very large scale integration (VLSI) systems, 2023-10, Vol.31 (10), p.1-11

2023

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A High-Throughput Hardware Accelerator for Lossless Compression of a DDR4 Command Trace

IEEE transactions on very large scale integration (VLSI) systems, 2019-01, Vol.27 (1), p.92-102

2019

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Fully Digital, Standard-Cell-Based Multifunction Compute-in-Memory Arrays for Genome Sequencing

IEEE transactions on very large scale integration (VLSI) systems, 2024-01, Vol.32 (1), p.30-41

2024

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Full CMOS Circuit for Brain-Inspired Associative Memory With On-Chip Trainable Memristive STDP Synapse

IEEE transactions on very large scale integration (VLSI) systems, 2023-07, Vol.31 (7), p.1-11

2023

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X-Former: In-Memory Acceleration of Transformers

IEEE transactions on very large scale integration (VLSI) systems, 2023-08, Vol.31 (8), p.1223-1233

2023

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A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection

IEEE transactions on very large scale integration (VLSI) systems, 2019-08, Vol.27 (8), p.1861-1873

2019

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Approximate Memory Compression

IEEE transactions on very large scale integration (VLSI) systems, 2020-04, Vol.28 (4), p.980-991

2020

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Recursive Synaptic Bit Reuse: An Efficient Way to Increase Memory Capacity in Associative Memory

IEEE transactions on very large scale integration (VLSI) systems, 2019-04, Vol.27 (4), p.757-768

2019

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Accelerating Recurrent Neural Networks: A Memory-Efficient Approach

IEEE transactions on very large scale integration (VLSI) systems, 2017-10, Vol.25 (10), p.2763-2775

2017

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Development of a Short-Term to Long-Term Supervised Spiking Neural Network Processor

IEEE transactions on very large scale integration (VLSI) systems, 2020-11, Vol.28 (11), p.2410-2423

2020

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Vesti: Energy-Efficient In-Memory Computing Accelerator for Deep Neural Networks

IEEE transactions on very large scale integration (VLSI) systems, 2020-01, Vol.28 (1), p.48-61

2020

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VLSI Design of Light-Field Factorization for Dual-Layer Factored Display

IEEE transactions on very large scale integration (VLSI) systems, 2024-11, Vol.32 (11), p.2093-2106

2024

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High-Accuracy and Low-Multiplication Recursive Discrete Cosine Transform Algorithm Design and Its Realization in Mel-Scale Frequency Cepstral Coefficients

IEEE transactions on very large scale integration (VLSI) systems, 2024-11, Vol.32 (11), p.2139-2143

2024

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Mixed-Signal Computing for Deep Neural Network Inference

IEEE transactions on very large scale integration (VLSI) systems, 2021-01, Vol.29 (1), p.3-13

Murmann, Boris

2021

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Power-Aware Neuromorphic Architecture With Partial Voltage Scaling 3-D Stacking Synaptic Memory

IEEE transactions on very large scale integration (VLSI) systems, 2023-12, Vol.31 (12), p.2016-2029

2023

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A Flexible Wildcard-Pattern Matching Accelerator via Simultaneous Discrete Finite Automata

IEEE transactions on very large scale integration (VLSI) systems, 2017-12, Vol.25 (12), p.3302-3316

2017

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High-Performance FPGA-Based CNN Accelerator With Block-Floating-Point Arithmetic

IEEE transactions on very large scale integration (VLSI) systems, 2019-08, Vol.27 (8), p.1874-1885

2019

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Bias-Dependent Variation in FinFET SRAM

IEEE transactions on very large scale integration (VLSI) systems, 2020-05, Vol.28 (5), p.1341-1344

2020

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A Dynamic Longest Prefix Matching Content Addressable Memory for IP Routing

IEEE transactions on very large scale integration (VLSI) systems, 2011-06, Vol.19 (6), p.963-972

2011

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A Spintronics Memory PUF for Resilience Against Cloning Counterfeit

IEEE transactions on very large scale integration (VLSI) systems, 2019-11, Vol.27 (11), p.2511-2522

2019

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Self-Controlled High-Performance Precharge-Free Content-Addressable Memory

IEEE transactions on very large scale integration (VLSI) systems, 2017-08, Vol.25 (8), p.2388-2392

2017

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Dynamic Built-In Redundancy Analysis for Memory Repair

IEEE transactions on very large scale integration (VLSI) systems, 2019-10, Vol.27 (10), p.2365-2374

2019

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On Noise Stability and Robustness of Adversarially Trained Networks on NVM Crossbars

IEEE transactions on very large scale integration (VLSI) systems, 2022-10, Vol.30 (10), p.1448-1460

2022

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Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation

IEEE transactions on very large scale integration (VLSI) systems, 2016-01, Vol.24 (1), p.92-102

2016

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An Implementation of Reconfigurable Match Table for FPGA-Based Programmable Switches

H3DAtten: Heterogeneous 3-D Integrated Hybrid Analog and Digital Compute-in-Memory Accelerator for Vision Transformer Self-Attention

A High-Throughput Hardware Accelerator for Lossless Compression of a DDR4 Command Trace

Fully Digital, Standard-Cell-Based Multifunction Compute-in-Memory Arrays for Genome Sequencing

Full CMOS Circuit for Brain-Inspired Associative Memory With On-Chip Trainable Memristive STDP Synapse

X-Former: In-Memory Acceleration of Transformers

A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection

Approximate Memory Compression

Recursive Synaptic Bit Reuse: An Efficient Way to Increase Memory Capacity in Associative Memory

Accelerating Recurrent Neural Networks: A Memory-Efficient Approach

Development of a Short-Term to Long-Term Supervised Spiking Neural Network Processor

Vesti: Energy-Efficient In-Memory Computing Accelerator for Deep Neural Networks

VLSI Design of Light-Field Factorization for Dual-Layer Factored Display

High-Accuracy and Low-Multiplication Recursive Discrete Cosine Transform Algorithm Design and Its Realization in Mel-Scale Frequency Cepstral Coefficients

Mixed-Signal Computing for Deep Neural Network Inference

Power-Aware Neuromorphic Architecture With Partial Voltage Scaling 3-D Stacking Synaptic Memory

A Flexible Wildcard-Pattern Matching Accelerator via Simultaneous Discrete Finite Automata

High-Performance FPGA-Based CNN Accelerator With Block-Floating-Point Arithmetic

Bias-Dependent Variation in FinFET SRAM

A Dynamic Longest Prefix Matching Content Addressable Memory for IP Routing

A Spintronics Memory PUF for Resilience Against Cloning Counterfeit

Self-Controlled High-Performance Precharge-Free Content-Addressable Memory

Dynamic Built-In Redundancy Analysis for Memory Repair

On Noise Stability and Robustness of Adversarially Trained Networks on NVM Crossbars

Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation

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