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In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands

IEEE transactions on very large scale integration (VLSI) systems, 2020-05, Vol.28 (5), p.1316-1320

2020

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IEEE_Xplore

Boosting NVDIMM Performance With a Lightweight Caching Algorithm

IEEE transactions on very large scale integration (VLSI) systems, 2018-08, Vol.26 (8), p.1518-1530

2018

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IEEE_Xplore

Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

IEEE transactions on very large scale integration (VLSI) systems, 2021-06, Vol.29 (6), p.1108-1121

2021

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IEEE_Xplore

Computing in Memory With Spin-Transfer Torque Magnetic RAM

IEEE transactions on very large scale integration (VLSI) systems, 2018-03, Vol.26 (3), p.470-483

2018

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IEEE_Xplore

High Restore Yield NVSRAM Structures With Dual Complementary RRAM Devices for High-Speed Applications

IEEE transactions on very large scale integration (VLSI) systems, 2023-04, Vol.31 (4), p.522-531

2023

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IEEE_Xplore

Compute-in-Memory Technologies and Architectures for Deep Learning Workloads

IEEE transactions on very large scale integration (VLSI) systems, 2022-11, Vol.30 (11), p.1-16

2022

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IEEE_Xplore

DURE: An Energy- and Resource-Efficient TCAM Architecture for FPGAs With Dynamic Updates

IEEE transactions on very large scale integration (VLSI) systems, 2019-06, Vol.27 (6), p.1298-1307

2019

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IEEE_Xplore

A 2-D Calibration Scheme for Resistive Nonvolatile Memories

IEEE transactions on very large scale integration (VLSI) systems, 2020-06, Vol.28 (6), p.1371-1377

2020

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IEEE_Xplore

Reuse-Distance-Aware Write-Intensity Prediction of Dataless Entries for Energy-Efficient Hybrid Caches

IEEE transactions on very large scale integration (VLSI) systems, 2018-10, Vol.26 (10), p.1881-1894

2018

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IEEE_Xplore

PFHA: A Novel Page Migration Algorithm for Hybrid Memory Embedded Systems

IEEE transactions on very large scale integration (VLSI) systems, 2021-10, Vol.29 (10), p.1685-1692

2021

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IEEE_Xplore

Multibit Content Addressable Memory Design and Optimization Based on 3-D nand-Compatible IGZO Flash

IEEE transactions on very large scale integration (VLSI) systems, 2024, p.1-9

2024

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IEEE_Xplore

RA-Aware Fail Data Collection Architecture for Cost Reduction

IEEE transactions on very large scale integration (VLSI) systems, 2024-06, Vol.32 (6), p.1136-1149

2024

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IEEE_Xplore

PXNOR-BNN: In/With Spin-Orbit Torque MRAM Preset-XNOR Operation-Based Binary Neural Networks

IEEE transactions on very large scale integration (VLSI) systems, 2019-11, Vol.27 (11), p.2668-2679

2019

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IEEE_Xplore

An Efficient NVM-Based Architecture for Intermittent Computing Under Energy Constraints

IEEE transactions on very large scale integration (VLSI) systems, 2023-06, Vol.31 (6), p.725-737

2023

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IEEE_Xplore

ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs

IEEE transactions on very large scale integration (VLSI) systems, 2020-04, Vol.28 (4), p.1084-1088

2020

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IEEE_Xplore

True Random Number Generation Using Latency Variations of FRAM

IEEE transactions on very large scale integration (VLSI) systems, 2021-01, Vol.29 (1), p.14-23

2021

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IEEE_Xplore

A Fully Digital SRAM-Based Four-Layer In-Memory Computing Unit Achieving Multiplication Operations and Results Store

IEEE transactions on very large scale integration (VLSI) systems, 2023-06, Vol.31 (6), p.776-788

2023

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IEEE_Xplore

A 40-nm SONOS Digital CIM Using Simplified LUT Multiplier and Continuous Sample-Hold Sense Amplifier for AI Edge Inference

IEEE transactions on very large scale integration (VLSI) systems, 2023-12, Vol.31 (12), p.2044-2052

2023

Link zum Volltext
IEEE_Xplore

IMCRYPTO: An In-Memory Computing Fabric for AES Encryption and Decryption

IEEE transactions on very large scale integration (VLSI) systems, 2022-05, Vol.30 (5), p.553-565

2022

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IEEE_Xplore

Design Tradeoffs of Vertical RRAM-Based 3-D Cross-Point Array

IEEE transactions on very large scale integration (VLSI) systems, 2016-12, Vol.24 (12), p.3460-3467

2016

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IEEE_Xplore

An 8-Bit in Resistive Memory Computing Core With Regulated Passive Neuron and Bitline Weight Mapping

IEEE transactions on very large scale integration (VLSI) systems, 2022-04, Vol.30 (4), p.379-391

2022

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IEEE_Xplore

ReRAM-Based Processing-in-Memory Architecture for Recurrent Neural Network Acceleration

IEEE transactions on very large scale integration (VLSI) systems, 2018-12, Vol.26 (12), p.2781-2794

2018

Link zum Volltext
IEEE_Xplore

H3DAtten: Heterogeneous 3-D Integrated Hybrid Analog and Digital Compute-in-Memory Accelerator for Vision Transformer Self-Attention

IEEE transactions on very large scale integration (VLSI) systems, 2023-10, Vol.31 (10), p.1-11

2023

Link zum Volltext
IEEE_Xplore

A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement

IEEE transactions on very large scale integration (VLSI) systems, 2019-10, Vol.27 (10), p.2375-2386

2019

Link zum Volltext
IEEE_Xplore

Experimental Investigation of 4-kb RRAM Arrays Programming Conditions Suitable for TCAM

IEEE transactions on very large scale integration (VLSI) systems, 2018-12, Vol.26 (12), p.2599-2607

2018

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IEEE_Xplore

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In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands

Boosting NVDIMM Performance With a Lightweight Caching Algorithm

Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

Computing in Memory With Spin-Transfer Torque Magnetic RAM

High Restore Yield NVSRAM Structures With Dual Complementary RRAM Devices for High-Speed Applications

Compute-in-Memory Technologies and Architectures for Deep Learning Workloads

DURE: An Energy- and Resource-Efficient TCAM Architecture for FPGAs With Dynamic Updates

A 2-D Calibration Scheme for Resistive Nonvolatile Memories

Reuse-Distance-Aware Write-Intensity Prediction of Dataless Entries for Energy-Efficient Hybrid Caches

PFHA: A Novel Page Migration Algorithm for Hybrid Memory Embedded Systems

Multibit Content Addressable Memory Design and Optimization Based on 3-D nand-Compatible IGZO Flash

RA-Aware Fail Data Collection Architecture for Cost Reduction

PXNOR-BNN: In/With Spin-Orbit Torque MRAM Preset-XNOR Operation-Based Binary Neural Networks

An Efficient NVM-Based Architecture for Intermittent Computing Under Energy Constraints

ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs

True Random Number Generation Using Latency Variations of FRAM

A Fully Digital SRAM-Based Four-Layer In-Memory Computing Unit Achieving Multiplication Operations and Results Store

A 40-nm SONOS Digital CIM Using Simplified LUT Multiplier and Continuous Sample-Hold Sense Amplifier for AI Edge Inference

IMCRYPTO: An In-Memory Computing Fabric for AES Encryption and Decryption

Design Tradeoffs of Vertical RRAM-Based 3-D Cross-Point Array

An 8-Bit in Resistive Memory Computing Core With Regulated Passive Neuron and Bitline Weight Mapping

ReRAM-Based Processing-in-Memory Architecture for Recurrent Neural Network Acceleration

H3DAtten: Heterogeneous 3-D Integrated Hybrid Analog and Digital Compute-in-Memory Accelerator for Vision Transformer Self-Attention

A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement

Experimental Investigation of 4-kb RRAM Arrays Programming Conditions Suitable for TCAM

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