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In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands

IEEE transactions on very large scale integration (VLSI) systems, 2020-05, Vol.28 (5), p.1316-1320

2020

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Multibit Content Addressable Memory Design and Optimization Based on 3-D nand-Compatible IGZO Flash

IEEE transactions on very large scale integration (VLSI) systems, 2024-08, Vol.32 (8), p.1380-1388

2024

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Data Allocation Optimization for Hybrid Scratch Pad Memory With SRAM and Nonvolatile Memory

IEEE transactions on very large scale integration (VLSI) systems, 2013-06, Vol.21 (6), p.1094-1102

2013

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Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage and Computing In-Memory

IEEE transactions on very large scale integration (VLSI) systems, 2020-12, Vol.28 (12), p.2636-2649

2020

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Endurance-Aware Compiler for 3-D Stackable FeRAM as Global Buffer in TPU-Like Architecture

IEEE transactions on very large scale integration (VLSI) systems, 2024-09, Vol.32 (9), p.1696-1703

2024

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Resource-Efficient SRAM-Based Ternary Content Addressable Memory

IEEE transactions on very large scale integration (VLSI) systems, 2017-04, Vol.25 (4), p.1583-1587

2017

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Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

IEEE transactions on very large scale integration (VLSI) systems, 2021-06, Vol.29 (6), p.1108-1121

2021

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An Implementation of Reconfigurable Match Table for FPGA-Based Programmable Switches

IEEE transactions on very large scale integration (VLSI) systems, 2024-11, Vol.32 (11), p.2121-2134

2024

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ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management and Data Organization for Deep Neural Network Accelerators

IEEE transactions on very large scale integration (VLSI) systems, 2021-04, Vol.29 (4), p.702-715

2021

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Computing in Memory With Spin-Transfer Torque Magnetic RAM

IEEE transactions on very large scale integration (VLSI) systems, 2018-03, Vol.26 (3), p.470-483

2018

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Compute-in-Memory Technologies and Architectures for Deep Learning Workloads

IEEE transactions on very large scale integration (VLSI) systems, 2022-11, Vol.30 (11), p.1-16

2022

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Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines

IEEE transactions on very large scale integration (VLSI) systems, 2011-08, Vol.19 (8), p.1407-1417

2011

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DURE: An Energy- and Resource-Efficient TCAM Architecture for FPGAs With Dynamic Updates

IEEE transactions on very large scale integration (VLSI) systems, 2019-06, Vol.27 (6), p.1298-1307

2019

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MCAIMem: A Mixed SRAM and eDRAM Cell for Area and Energy-Efficient On-Chip AI Memory

IEEE transactions on very large scale integration (VLSI) systems, 2024-11, Vol.32 (11), p.2023-2036

2024

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High Restore Yield NVSRAM Structures With Dual Complementary RRAM Devices for High-Speed Applications

IEEE transactions on very large scale integration (VLSI) systems, 2023-04, Vol.31 (4), p.522-531

2023

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Boosting NVDIMM Performance With a Lightweight Caching Algorithm

IEEE transactions on very large scale integration (VLSI) systems, 2018-08, Vol.26 (8), p.1518-1530

2018

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Reuse-Distance-Aware Write-Intensity Prediction of Dataless Entries for Energy-Efficient Hybrid Caches

IEEE transactions on very large scale integration (VLSI) systems, 2018-10, Vol.26 (10), p.1881-1894

2018

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PXNOR-BNN: In/With Spin-Orbit Torque MRAM Preset-XNOR Operation-Based Binary Neural Networks

IEEE transactions on very large scale integration (VLSI) systems, 2019-11, Vol.27 (11), p.2668-2679

2019

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A 2-D Calibration Scheme for Resistive Nonvolatile Memories

IEEE transactions on very large scale integration (VLSI) systems, 2020-06, Vol.28 (6), p.1371-1377

2020

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PFHA: A Novel Page Migration Algorithm for Hybrid Memory Embedded Systems

IEEE transactions on very large scale integration (VLSI) systems, 2021-10, Vol.29 (10), p.1685-1692

2021

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Dynamic Adjustment of Storage Class Memory Capacity in Memory-Resource Disaggregated Hybrid Storage With SCM and NAND Flash Memory

IEEE transactions on very large scale integration (VLSI) systems, 2019-08, Vol.27 (8), p.1799-1810

2019

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Design of Spin-Torque Transfer Magnetoresistive RAM and CAM/TCAM with High Sensing and Search Speed

IEEE transactions on very large scale integration (VLSI) systems, 2010-01, Vol.18 (1), p.66-74

2010

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ReRAM-Based Processing-in-Memory Architecture for Recurrent Neural Network Acceleration

IEEE transactions on very large scale integration (VLSI) systems, 2018-12, Vol.26 (12), p.2781-2794

2018

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RA-Aware Fail Data Collection Architecture for Cost Reduction

IEEE transactions on very large scale integration (VLSI) systems, 2024-06, Vol.32 (6), p.1136-1149

2024

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IPOCIM: Artificial Intelligent Architecture Design Space Exploration With Scalable Ping-Pong Computing-in-Memory Macro

IEEE transactions on very large scale integration (VLSI) systems, 2024-02, Vol.32 (2), p.256-268

2024

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In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands

Multibit Content Addressable Memory Design and Optimization Based on 3-D nand-Compatible IGZO Flash

Data Allocation Optimization for Hybrid Scratch Pad Memory With SRAM and Nonvolatile Memory

Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage and Computing In-Memory

Endurance-Aware Compiler for 3-D Stackable FeRAM as Global Buffer in TPU-Like Architecture

Resource-Efficient SRAM-Based Ternary Content Addressable Memory

Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

An Implementation of Reconfigurable Match Table for FPGA-Based Programmable Switches

ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management and Data Organization for Deep Neural Network Accelerators

Computing in Memory With Spin-Transfer Torque Magnetic RAM

Compute-in-Memory Technologies and Architectures for Deep Learning Workloads

Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines

DURE: An Energy- and Resource-Efficient TCAM Architecture for FPGAs With Dynamic Updates

MCAIMem: A Mixed SRAM and eDRAM Cell for Area and Energy-Efficient On-Chip AI Memory

High Restore Yield NVSRAM Structures With Dual Complementary RRAM Devices for High-Speed Applications

Boosting NVDIMM Performance With a Lightweight Caching Algorithm

Reuse-Distance-Aware Write-Intensity Prediction of Dataless Entries for Energy-Efficient Hybrid Caches

PXNOR-BNN: In/With Spin-Orbit Torque MRAM Preset-XNOR Operation-Based Binary Neural Networks

A 2-D Calibration Scheme for Resistive Nonvolatile Memories

PFHA: A Novel Page Migration Algorithm for Hybrid Memory Embedded Systems

Dynamic Adjustment of Storage Class Memory Capacity in Memory-Resource Disaggregated Hybrid Storage With SCM and NAND Flash Memory

Design of Spin-Torque Transfer Magnetoresistive RAM and CAM/TCAM with High Sensing and Search Speed

ReRAM-Based Processing-in-Memory Architecture for Recurrent Neural Network Acceleration

RA-Aware Fail Data Collection Architecture for Cost Reduction

IPOCIM: Artificial Intelligent Architecture Design Space Exploration With Scalable Ping-Pong Computing-in-Memory Macro

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