UB Paderborn / Katalog / Suche / in CDI

1 – 25 von 27

Sortiert nach

Low-temperature electrical characterization of junctionless transistors

Solid-state electronics, 2013-02, Vol.80, p.135-141

2013

Link zum Volltext

Verfügbarkeit prüfen

Low-frequency noise behavior of junctionless transistors compared to inversion-mode transistors

Solid-state electronics, 2013-03, Vol.81, p.101-104

2013

Link zum Volltext

Verfügbarkeit prüfen

Effects of channel width variation on electrical characteristics of tri-gate Junctionless transistors

Solid-state electronics, 2013-03, Vol.81, p.58-62

2013

Link zum Volltext

Verfügbarkeit prüfen

Influence of interface traps position along channel in the low-frequency noise of junctionless nanowire transistors

Solid-state electronics, 2024-02, Vol.212, p.108835, Article 108835

2024

Link zum Volltext

Verfügbarkeit prüfen

Comprehensive evaluation of gate-induced drain leakage in SOI stacked nanowire nMOSFETs operating in high-temperatures

Solid-state electronics, 2024-04, Vol.214, p.108865, Article 108865

2024

Link zum Volltext

Verfügbarkeit prüfen

Interface traps density extraction through transient measurements in junctionless transistors

Solid-state electronics, 2022-08, Vol.194, p.108302, Article 108302

2022

Link zum Volltext

Verfügbarkeit prüfen

Experimental assessment of gate-induced drain leakage in SOI stacked nanowire and nanosheet nMOSFETs at high temperatures

Solid-state electronics, 2023-10, Vol.208, p.108716, Article 108716

2023

Link zum Volltext

Verfügbarkeit prüfen

Influence of interface traps density and temperature variation on the NBTI effect in p-Type junctionless nanowire transistors

Solid-state electronics, 2021-12, Vol.186, p.108097, Article 108097

2021

Link zum Volltext

Verfügbarkeit prüfen

Influence of fin width variation on the electrical characteristics of n-type junctionless nanowire transistors at high temperatures

Solid-state electronics, 2021-11, Vol.185, p.108072, Article 108072

2021

Link zum Volltext

Verfügbarkeit prüfen

Electrical characteristics of n-type vertically stacked nanowires operating up to 600 K

Solid-state electronics, 2022-08, Vol.194, p.108337, Article 108337

2022

Link zum Volltext

Verfügbarkeit prüfen

Channel width dependent subthreshold operation of tri-gate junctionless transistors

Solid-state electronics, 2020-09, Vol.171, p.107860, Article 107860

2020

Link zum Volltext

Verfügbarkeit prüfen

Impact of series resistance on the drain current variability in inversion mode and junctionless nanowire transistors

Solid-state electronics, 2023-10, Vol.208, p.108737, Article 108737

2023

Link zum Volltext

Verfügbarkeit prüfen

Bias dependent physics-based model of low-frequency noise for nanowire type gate-all-around MOSFETs

Solid-state electronics, 2022-03, Vol.189, p.108223, Article 108223

2022

Link zum Volltext

Verfügbarkeit prüfen

Electrical characterization of stacked SOI nanowires at low temperatures

Solid-state electronics, 2022-05, Vol.191, p.108260, Article 108260

2022

Link zum Volltext

Verfügbarkeit prüfen

Low temperature influence on performance and transport of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs

Solid-state electronics, 2019-09, Vol.159, p.83-89

2019

Link zum Volltext

Verfügbarkeit prüfen

Analog characteristics of n-type vertically stacked nanowires

Solid-state electronics, 2021-11, Vol.185, p.108127, Article 108127

2021

Link zum Volltext

Verfügbarkeit prüfen

Impact of series resistance on the operation of junctionless transistors

Solid-state electronics, 2017-03, Vol.129, p.103-107

2017

Link zum Volltext

Verfügbarkeit prüfen

Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100K

Solid-state electronics, 2017-02, Vol.128, p.60-66

2017

Link zum Volltext

Verfügbarkeit prüfen

Back-gate effects and mobility characterization in junctionless transistor

Solid-state electronics, 2016-11, Vol.125, p.154-160

2016

Link zum Volltext

Verfügbarkeit prüfen

Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs

Solid-state electronics, 2018-11, Vol.149, p.62-70

2018

Link zum Volltext

Verfügbarkeit prüfen

Series resistance in different operation regime of junctionless transistors

Solid-state electronics, 2018-03, Vol.141, p.92-95

2018

Link zum Volltext

Verfügbarkeit prüfen

Electrical characterization of vertically stacked p-FET SOI nanowires

Solid-state electronics, 2018-03, Vol.141, p.84-91

2018

Link zum Volltext

Verfügbarkeit prüfen

Behavior of subthreshold conduction in junctionless transistors

Solid-state electronics, 2016-10, Vol.124, p.58-63

2016

Link zum Volltext

Verfügbarkeit prüfen

Strain effect on mobility in nanowire MOSFETs down to 10 nm width: Geometrical effects and piezoresistive model

Solid-state electronics, 2016-11, Vol.125, p.175-181

2016

Link zum Volltext

Verfügbarkeit prüfen

Back biasing effects in tri-gate junctionless transistors

Solid-state electronics, 2013-09, Vol.87, p.74-79

2013

Link zum Volltext

Verfügbarkeit prüfen

1 – 25 von 27

Suche als RSS-Feed

Aktive Filter

KollektionSpringerLink (Online service)

Zeitschrift / SerieSolid-State Electronics

Suchergebnisse filtern

Filter anzeigen

Nur zeigen

Geprüft (Peer-Review)
(27)
Mit Volltextzugriff
(27)

Publikationsform

Artikel
(27)

Sprache

Englisch
(27)
Japanisch
(3)

Erscheinungsjahr

n.n

Thema

Engineering
(24)
Engineering, Electrical & Electronic
(24)
Physical Sciences
(24)
Physics
(24)
Physics, Applied
(24)
Physics, Condensed Matter
(24)
Science & Technology
(24)
Technology
(24)
Engineering Sciences
(12)
Micro And Nanotechnologies
(12)
Microelectronics
(12)
Junctionless Transistors
(7)
Applied Sciences
(5)
Electronics
(5)
Exact Sciences And Technology
(5)
Semiconductor Electronics. Microelectronics. Optoelectronics. Solid State Devices
(5)
Soi
(5)
Transistors
(5)
Flat-Band Voltage
(4)
Condensed Matter Physics
(3)

15 weitere anzeigen...

Weniger anzeigen...

Kollektion

Menü

Weitere Dienste

Einstellungen

Low-temperature electrical characterization of junctionless transistors

Low-frequency noise behavior of junctionless transistors compared to inversion-mode transistors

Effects of channel width variation on electrical characteristics of tri-gate Junctionless transistors

Influence of interface traps position along channel in the low-frequency noise of junctionless nanowire transistors

Comprehensive evaluation of gate-induced drain leakage in SOI stacked nanowire nMOSFETs operating in high-temperatures

Interface traps density extraction through transient measurements in junctionless transistors

Experimental assessment of gate-induced drain leakage in SOI stacked nanowire and nanosheet nMOSFETs at high temperatures

Influence of interface traps density and temperature variation on the NBTI effect in p-Type junctionless nanowire transistors

Influence of fin width variation on the electrical characteristics of n-type junctionless nanowire transistors at high temperatures

Electrical characteristics of n-type vertically stacked nanowires operating up to 600 K

Channel width dependent subthreshold operation of tri-gate junctionless transistors

Impact of series resistance on the drain current variability in inversion mode and junctionless nanowire transistors

Bias dependent physics-based model of low-frequency noise for nanowire type gate-all-around MOSFETs

Electrical characterization of stacked SOI nanowires at low temperatures

Low temperature influence on performance and transport of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs

Analog characteristics of n-type vertically stacked nanowires

Impact of series resistance on the operation of junctionless transistors

Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100K

Back-gate effects and mobility characterization in junctionless transistor

Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs

Series resistance in different operation regime of junctionless transistors

Electrical characterization of vertically stacked p-FET SOI nanowires

Behavior of subthreshold conduction in junctionless transistors

Strain effect on mobility in nanowire MOSFETs down to 10 nm width: Geometrical effects and piezoresistive model

Back biasing effects in tri-gate junctionless transistors

Aktive Filter

Suchergebnisse filtern