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Gibbon: An Efficient Co-Exploration Framework of NN model and Processing-In-Memory Architecture

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-11, Vol.42 (11), p.1-1

2023

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CURIOUS: Efficient Neural Architecture Search Based on a Performance Predictor and Evolutionary Search

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-11, Vol.41 (11), p.4975-4990

2022

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IEEE_Xplore

M²NAS: Joint Neural Architecture Optimization System With Network Transmission

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-08, Vol.42 (8), p.2631-2642

2023

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IEEE_Xplore

TUTOR: Training Neural Networks Using Decision Rules as Model Priors

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-02, Vol.42 (2), p.483-496

2023

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IEEE_Xplore

Nearly-2-SAT Solutions for Segmented-Channel Routing

IEEE transactions on computer-aided design of integrated circuits and systems, 2016-01, Vol.35 (1), p.128-140

2016

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IEEE_Xplore

A Novel Implementation Methodology for Error Correction Codes on a Neuromorphic Architecture

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-12, Vol.42 (12), p.1-1

2023

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IEEE_Xplore

Distributed Deep Learning Optimization of Heat Equation Inverse Problem Solvers

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-12, Vol.42 (12), p.1-1

2023

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IEEE_Xplore

Realization and Hardware Implementation of Gating Units for Long Short Term Memory Network using Hyperbolic Sine Functions

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-12, Vol.42 (12), p.1-1

2023

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IEEE_Xplore

Synthesis of Active Cell Balancing Architectures for Battery Packs

IEEE transactions on computer-aided design of integrated circuits and systems, 2016-11, Vol.35 (11), p.1876-1889

2016

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IEEE_Xplore

High Throughput Data Mapping for Coarse-Grained Reconfigurable Architectures

IEEE transactions on computer-aided design of integrated circuits and systems, 2011-11, Vol.30 (11), p.1599-1609

2011

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IEEE_Xplore

Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs

IEEE transactions on computer-aided design of integrated circuits and systems, 2011-11, Vol.30 (11), p.1705-1718

2011

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IEEE_Xplore

Unleashing the Potential of Sparse DNNs Through Synergistic Hardware-Sparsity Co-Design

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-04, Vol.42 (4), p.1147-1160

2023

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IEEE_Xplore

PolyPUF: Physically Secure Self-Divergence

IEEE transactions on computer-aided design of integrated circuits and systems, 2016-07, Vol.35 (7), p.1053-1066

2016

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IEEE_Xplore

Accelerating Graph Neural Network Training on ReRAM-Based PIM Architectures via Graph and Model Pruning

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-08, Vol.42 (8), p.2703-2716

2023

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IEEE_Xplore

Modeling and Simulation of Circuit-Level Nonidealities for an Analog Computing Design Approach With Application to EEG Feature Extraction

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-01, Vol.42 (1), p.229-242

2023

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IEEE_Xplore

MoRS: An Approximate Fault Modeling Framework for Reduced-Voltage SRAMs

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-06, Vol.41 (6), p.1663-1673

2022

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IEEE_Xplore

Physical-Layer Modeling and System-Level Design of Chip-Scale Photonic Interconnection Networks

IEEE transactions on computer-aided design of integrated circuits and systems, 2011-10, Vol.30 (10), p.1507-1520

2011

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IEEE_Xplore

Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems

IEEE transactions on computer-aided design of integrated circuits and systems, 2010-06, Vol.29 (6), p.911-924

2010

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IEEE_Xplore

CKFO: Convolution Kernel First Operated Algorithm With Applications in Memristor-Based Convolutional Neural Network

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-08, Vol.40 (8), p.1640-1647

2021

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IEEE_Xplore

A Data-Driven Verilog-A ReRAM Model

IEEE transactions on computer-aided design of integrated circuits and systems, 2018-12, Vol.37 (12), p.3151-3162

2018

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IEEE_Xplore

Mining Requirements From Closed-Loop Control Models

IEEE transactions on computer-aided design of integrated circuits and systems, 2015-11, Vol.34 (11), p.1704-1717

2015

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IEEE_Xplore

High-Level Synthesis for FPGAs: From Prototyping to Deployment

IEEE transactions on computer-aided design of integrated circuits and systems, 2011-04, Vol.30 (4), p.473-491

2011

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IEEE_Xplore

Recomputing with Permuted Operands: A Concurrent Error Detection Approach

IEEE transactions on computer-aided design of integrated circuits and systems, 2013-10, Vol.32 (10), p.1595-1608

2013

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IEEE_Xplore

QMDDs: Efficient Quantum Function Representation and Manipulation

IEEE transactions on computer-aided design of integrated circuits and systems, 2016-01, Vol.35 (1), p.86-99

2016

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IEEE_Xplore

Evaluating Fast Algorithms for Convolutional Neural Networks on FPGAs

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-04, Vol.39 (4), p.857-870

2020

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Gibbon: An Efficient Co-Exploration Framework of NN model and Processing-In-Memory Architecture

CURIOUS: Efficient Neural Architecture Search Based on a Performance Predictor and Evolutionary Search

M²NAS: Joint Neural Architecture Optimization System With Network Transmission

TUTOR: Training Neural Networks Using Decision Rules as Model Priors

Nearly-2-SAT Solutions for Segmented-Channel Routing

A Novel Implementation Methodology for Error Correction Codes on a Neuromorphic Architecture

Distributed Deep Learning Optimization of Heat Equation Inverse Problem Solvers

Realization and Hardware Implementation of Gating Units for Long Short Term Memory Network using Hyperbolic Sine Functions

Synthesis of Active Cell Balancing Architectures for Battery Packs

High Throughput Data Mapping for Coarse-Grained Reconfigurable Architectures

Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs

Unleashing the Potential of Sparse DNNs Through Synergistic Hardware-Sparsity Co-Design

PolyPUF: Physically Secure Self-Divergence

Accelerating Graph Neural Network Training on ReRAM-Based PIM Architectures via Graph and Model Pruning

Modeling and Simulation of Circuit-Level Nonidealities for an Analog Computing Design Approach With Application to EEG Feature Extraction

MoRS: An Approximate Fault Modeling Framework for Reduced-Voltage SRAMs

Physical-Layer Modeling and System-Level Design of Chip-Scale Photonic Interconnection Networks

Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems

CKFO: Convolution Kernel First Operated Algorithm With Applications in Memristor-Based Convolutional Neural Network

A Data-Driven Verilog-A ReRAM Model

Mining Requirements From Closed-Loop Control Models

High-Level Synthesis for FPGAs: From Prototyping to Deployment

Recomputing with Permuted Operands: A Concurrent Error Detection Approach

QMDDs: Efficient Quantum Function Representation and Manipulation

Evaluating Fast Algorithms for Convolutional Neural Networks on FPGAs

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