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Hybrid shared-memory and message-passing multiprocessor system-on-chip for UWB MAC layer

IET computers & digital techniques, 2017-01, Vol.11 (1), p.8-15

2017

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Exploiting memory allocations in clusterised many-core architectures

IET computers & digital techniques, 2019-07, Vol.13 (4), p.302-311

2019

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CUDA memory optimisation strategies for motion estimation

IET computers & digital techniques, 2019-01, Vol.13 (1), p.20-27

2019

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Fighting stochastic variability in a D-type flip-flop with transistor-level reconfiguration

IET computers & digital techniques, 2015-07, Vol.9 (4), p.190-196

2015

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Survey on memory management techniques in heterogeneous computing systems

IET computers & digital techniques, 2020-03, Vol.14 (2), p.47-60

2020

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High throughput fault-resilient AES architecture

IET computers & digital techniques, 2019-07, Vol.13 (4), p.312-323

2019

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Event‐based high throughput computing: A series of case studies on a massively parallel softcore machine

IET computers & digital techniques, 2023-01, Vol.17 (1), p.29-42

2023

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Inexact-aware architecture design for ultra-low power bio-signal analysis

IET computers & digital techniques, 2016-11, Vol.10 (6), p.306-314

2016

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Partitioned security processor architecture on FPGA platform

IET computers & digital techniques, 2018-09, Vol.12 (5), p.216-226

2018

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Accelerating the SM3 hash algorithm with CPU‐FPGA Co‐Designed architecture

IET computers & digital techniques, 2021-11, Vol.15 (6), p.427-436

2021

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Area and power-efficient variable-length fast Fourier transform for MR-OFDM physical layer of IEEE 802.15.4-g

IET computers & digital techniques, 2020-09, Vol.14 (5), p.193-200

2020

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Accelerating Deep Neural Networks implementation: A survey

IET computers & digital techniques, 2021-03, Vol.15 (2), p.79-96

2021

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High-performance elliptic curve cryptography processor over NIST prime fields

IET computers & digital techniques, 2017-01, Vol.11 (1), p.33-42

2017

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Image feature extraction algorithm based on CUDA architecture: case study GFD and GCFD

IET computers & digital techniques, 2017-07, Vol.11 (4), p.125-132

2017

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An integrated taxonomy of standard indicators for ranking and selecting supercomputers

IET computers & digital techniques, 2023-07, Vol.17 (3-4), p.162-179

2023

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In memory computation using quantum-dot cellular automata

IET computers & digital techniques, 2020-11, Vol.14 (6), p.336-343

2020

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A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits

IET computers & digital techniques, 2013-07, Vol.7 (4), p.167-181

2013

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Throughput/area optimised pipelined architecture for elliptic curve crypto processor

IET computers & digital techniques, 2019-09, Vol.13 (5), p.361-368

2019

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H.264/AVC high definition intra coding implementation on multiprocessor system on chip technology architecture

IET computers & digital techniques, 2015-09, Vol.9 (5), p.259-267

2015

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Unified multi-objective mapping and architecture customisation of networks-on-chip

IET computers & digital techniques, 2013-11, Vol.7 (6), p.282-293

2013

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Accuracy-aware processor customisation for fixed-point arithmetic

IET computers & digital techniques, 2016-01, Vol.10 (1), p.1-11

2016

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Efficient ASIC and FPGA implementation of cube architecture

IET computers & digital techniques, 2017-01, Vol.11 (1), p.43-49

2017

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An Efficient RTL Design for a Wearable Brain–Computer Interface

IET computers & digital techniques, 2024-03, Vol.2024

2024

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Radix-43 based two-dimensional FFT architecture with efficient data reordering scheme

IET computers & digital techniques, 2019-03, Vol.13 (2), p.78-86

2019

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Adaptive Shrink and Shard Architecture Design for Blockchain Storage Efficiency

IET computers & digital techniques, 2024-02, Vol.2024

2024

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Hybrid shared-memory and message-passing multiprocessor system-on-chip for UWB MAC layer

Exploiting memory allocations in clusterised many-core architectures

CUDA memory optimisation strategies for motion estimation

Fighting stochastic variability in a D-type flip-flop with transistor-level reconfiguration

Survey on memory management techniques in heterogeneous computing systems

High throughput fault-resilient AES architecture

Event‐based high throughput computing: A series of case studies on a massively parallel softcore machine

Inexact-aware architecture design for ultra-low power bio-signal analysis

Partitioned security processor architecture on FPGA platform

Accelerating the SM3 hash algorithm with CPU‐FPGA Co‐Designed architecture

Area and power-efficient variable-length fast Fourier transform for MR-OFDM physical layer of IEEE 802.15.4-g

Accelerating Deep Neural Networks implementation: A survey

High-performance elliptic curve cryptography processor over NIST prime fields

Image feature extraction algorithm based on CUDA architecture: case study GFD and GCFD

An integrated taxonomy of standard indicators for ranking and selecting supercomputers

In memory computation using quantum-dot cellular automata

A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits

Throughput/area optimised pipelined architecture for elliptic curve crypto processor

H.264/AVC high definition intra coding implementation on multiprocessor system on chip technology architecture

Unified multi-objective mapping and architecture customisation of networks-on-chip

Accuracy-aware processor customisation for fixed-point arithmetic

Efficient ASIC and FPGA implementation of cube architecture

An Efficient RTL Design for a Wearable Brain–Computer Interface

Radix-43 based two-dimensional FFT architecture with efficient data reordering scheme

Adaptive Shrink and Shard Architecture Design for Blockchain Storage Efficiency

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