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Revisiting RowHammer: an experimental analysis of modern DRAM devices and mitigation techniques

2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA), 2020, p.638-651

2020

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Hardware architecture and software stack for PIM based on commercial DRAM technology

Proceedings of the 48th Annual International Symposium on Computer Architecture, 2021, p.43-56

2021

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FPGA-Based Sparse Matrix Multiplication Accelerators: From State-of-the-art to Future Opportunities

ACM transactions on reconfigurable technology and systems, 2024-08

2024

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An experimental study of data retention behavior in modern DRAM devices: implications for retention time profiling mechanisms

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013, p.60-71

2013

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Uncovering In-DRAM RowHammer Protection Mechanisms:A New Methodology, Custom RowHammer Patterns, and Implications

MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021, p.1198-1213

2021

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Introduction to the Special Section on FPGA 2023

ACM transactions on reconfigurable technology and systems, 2024-09, Vol.17 (3), p.1-2, Article 43

2024

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A new stochastic computing multiplier with application to deep convolutional neural networks

2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC), 2017, p.1-6

2017

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A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses

MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021, p.1182-1197

2021

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MuonTrap: preventing cross-domain spectre-like attacks by capturing speculative state

2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA), 2020, p.132-144

2020

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A Post-training Quantization Method for the Design of Fixed-Point-Based FPGA/ASIC Hardware Accelerators for LSTM/GRU Algorithms

Computational intelligence and neuroscience, 2022-05, Vol.2022, p.9485933-13

2022

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TaintDroid: An Information-Flow Tracking System for Realtime Privacy Monitoring on Smartphones

ACM transactions on computer systems, 2014-06, Vol.32 (2), p.1-29

2014

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The reach profiler (REAPER): Enabling the mitigation of DRAM retention failures via profiling at aggressive conditions

2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA), 2017, p.255-268

2017

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Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013, p.48-59

2013

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ArchShield: architectural framework for assisting DRAM scaling by tolerating high error rates

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013, p.72-83

2013

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Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology

2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2017, p.273-287

2017

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QUAC-TRNG: high-throughput true random number generation using quadruple row activation in commodity DRAM chips

2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA), 2021, p.944-957

2021

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Random Fill Cache Architecture

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014, p.203-215

2014

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Synthesis and Optimization of Reversible Circuits—A Survey

ACM computing surveys, 2013-02, Vol.45 (2), p.1-34

2013

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PROTECTS: Progressive Rtl Obfuscation with ThrEshold Control Technique during architectural Synthesis

ACM transactions on design automation of electronic systems, 2024-10

2024

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Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks

2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2016, p.1-6

2016

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Bouquet of instruction pointers: instruction pointer classifier-based spatial hardware prefetching

2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA), 2020, p.118-131

2020

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Graph-OPU: A highly flexible FPGA-Based Overlay Processor for Graph Neural Networks

ACM transactions on reconfigurable technology and systems, 2024-09

2024

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CLR-DRAM: a low-cost DRAM architecture enabling dynamic capacity-latency trade-off

2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA), 2020, p.666-679

2020

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Security analysis of integrated circuit camouflaging

Proceedings of the 2013 ACM SIGSAC conference on Computer & communications security, 2013, p.709-720

2013

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GraphQ: Scalable PIM-Based Graph Processing

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019, p.712-725

2019

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Revisiting RowHammer: an experimental analysis of modern DRAM devices and mitigation techniques

Hardware architecture and software stack for PIM based on commercial DRAM technology

FPGA-Based Sparse Matrix Multiplication Accelerators: From State-of-the-art to Future Opportunities

An experimental study of data retention behavior in modern DRAM devices: implications for retention time profiling mechanisms

Uncovering In-DRAM RowHammer Protection Mechanisms:A New Methodology, Custom RowHammer Patterns, and Implications

Introduction to the Special Section on FPGA 2023

A new stochastic computing multiplier with application to deep convolutional neural networks

A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses

MuonTrap: preventing cross-domain spectre-like attacks by capturing speculative state

A Post-training Quantization Method for the Design of Fixed-Point-Based FPGA/ASIC Hardware Accelerators for LSTM/GRU Algorithms

TaintDroid: An Information-Flow Tracking System for Realtime Privacy Monitoring on Smartphones

The reach profiler (REAPER): Enabling the mitigation of DRAM retention failures via profiling at aggressive conditions

Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems

ArchShield: architectural framework for assisting DRAM scaling by tolerating high error rates

Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology

QUAC-TRNG: high-throughput true random number generation using quadruple row activation in commodity DRAM chips

Random Fill Cache Architecture

Synthesis and Optimization of Reversible Circuits—A Survey

PROTECTS: Progressive Rtl Obfuscation with ThrEshold Control Technique during architectural Synthesis

Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks

Bouquet of instruction pointers: instruction pointer classifier-based spatial hardware prefetching

Graph-OPU: A highly flexible FPGA-Based Overlay Processor for Graph Neural Networks

CLR-DRAM: a low-cost DRAM architecture enabling dynamic capacity-latency trade-off

Security analysis of integrated circuit camouflaging

GraphQ: Scalable PIM-Based Graph Processing

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