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Characterization of In-Cone Logic Locking Resiliency Against the SAT Attack

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-08, Vol.39 (8), p.1607-1620

2020

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Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance

IEEE transactions on electron devices, 2009-09, Vol.56 (9), p.1873-1881

2009

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IEEE_Xplore

Synthesis of Hidden State Transitions for Sequential Logic Locking

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-01, Vol.40 (1), p.11-23

2021

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IEEE_Xplore

Increased Output Corruption and Structural Attack Resilience for SAT Attack Secure Logic Locking

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-01, Vol.40 (1), p.38-51

2021

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IEEE_Xplore

Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits

Microelectronics, 2010, Vol.41 (1), p.9-16

2010

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On-Chip Power Supply Noise Suppression Through Hyperabrupt Junction Varactors

IEEE transactions on very large scale integration (VLSI) systems, 2018-11, Vol.26 (11), p.2230-2240

2018

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IEEE_Xplore

Graph Representation Learning for Parasitic Impedance Prediction of the Interconnect

2023 IEEE International Symposium on Circuits and Systems (ISCAS), 2023, p.1-5

2023

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IEEE_Xplore

A Power Side-Channel Attack on Flash ADC

2023 IEEE International Symposium on Circuits and Systems (ISCAS), 2023, p.1-5

2023

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IEEE_Xplore

Synthesis of Coupling Capacitance Based Hidden State Transitions for Sequential Logic Locking

2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2022, p.1734-1738

2022

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IEEE_Xplore

A 3-D Integrated Intrachip Free-Space Optical Interconnect for Many-Core Chips

IEEE photonics technology letters, 2011-02, Vol.23 (3), p.164-166

2011

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IEEE_Xplore

Increasing the SAT Attack Resiliency of In-Cone Logic Locking

2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019, p.1-5

2019

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IEEE_Xplore

Reducing Logic Locking Key Leakage through the Scan Chain

2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, p.1-5

2020

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IEEE_Xplore

Dynamic differential signaling based logic families for robust ultra-low power near-threshold computing

Microelectronics, 2020-08, Vol.102, p.104801, Article 104801

2020

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Smart Grid on Chip: Work Load-Balanced On-Chip Power Delivery

IEEE transactions on very large scale integration (VLSI) systems, 2017-09, Vol.25 (9), p.2538-2551

2017

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IEEE_Xplore

Applying Swarm Intelligence to Distributed On-Chip Power Management

2019 IEEE 37th International Conference on Computer Design (ICCD), 2019, p.532-540

2019

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An intra-chip free-space optical interconnect

Proceedings of the 37th annual international symposium on computer architecture, 2010, p.94-105

2010

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Modeling SAT-Attack Search Complexity

2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, p.1-5

2020

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IEEE_Xplore

The intratumoral CXCR3 chemokine system is predictive of chemotherapy response in human bladder cancer

Science translational medicine, 2021-01, Vol.13 (576)

2021

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Experimental Analysis of Thermal Coupling in 3-D Integrated Circuits

IEEE transactions on very large scale integration (VLSI) systems, 2015-10, Vol.23 (10), p.2077-2089

2015

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IEEE_Xplore

ElasticCore: A Dynamic Heterogeneous Platform With Joint Core and Voltage/Frequency Scaling

IEEE transactions on very large scale integration (VLSI) systems, 2018-02, Vol.26 (2), p.249-261

2018

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IEEE_Xplore

3-D integrated heterogeneous intra-chip free-space optical interconnect

Optics express, 2012-02, Vol.20 (4), p.4331-4345

2012

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Power Noise in TSV-Based 3-D Integrated Circuits

IEEE journal of solid-state circuits, 2013-02, Vol.48 (2), p.587-597

2013

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IEEE_Xplore

Power supply voltage detection and clamping circuit for 3-D integrated circuits

2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2014, p.1-3

2014

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IEEE_Xplore

Machine Learning on the Thermal Side-Channel: Analysis of Accelerator-Rich Architectures

2018 IEEE 36th International Conference on Computer Design (ICCD), 2018, p.83-91

2018

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IEEE_Xplore

EDA-ML: Graph Representation Learning Framework for Digital IC Design Automation

2024 25th International Symposium on Quality Electronic Design (ISQED), 2024, p.1-7

2024

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IEEE_Xplore

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Characterization of In-Cone Logic Locking Resiliency Against the SAT Attack

Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance

Synthesis of Hidden State Transitions for Sequential Logic Locking

Increased Output Corruption and Structural Attack Resilience for SAT Attack Secure Logic Locking

Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits

On-Chip Power Supply Noise Suppression Through Hyperabrupt Junction Varactors

Graph Representation Learning for Parasitic Impedance Prediction of the Interconnect

A Power Side-Channel Attack on Flash ADC

Synthesis of Coupling Capacitance Based Hidden State Transitions for Sequential Logic Locking

A 3-D Integrated Intrachip Free-Space Optical Interconnect for Many-Core Chips

Increasing the SAT Attack Resiliency of In-Cone Logic Locking

Reducing Logic Locking Key Leakage through the Scan Chain

Dynamic differential signaling based logic families for robust ultra-low power near-threshold computing

Smart Grid on Chip: Work Load-Balanced On-Chip Power Delivery

Applying Swarm Intelligence to Distributed On-Chip Power Management

An intra-chip free-space optical interconnect

Modeling SAT-Attack Search Complexity

The intratumoral CXCR3 chemokine system is predictive of chemotherapy response in human bladder cancer

Experimental Analysis of Thermal Coupling in 3-D Integrated Circuits

ElasticCore: A Dynamic Heterogeneous Platform With Joint Core and Voltage/Frequency Scaling

3-D integrated heterogeneous intra-chip free-space optical interconnect

Power Noise in TSV-Based 3-D Integrated Circuits

Power supply voltage detection and clamping circuit for 3-D integrated circuits

Machine Learning on the Thermal Side-Channel: Analysis of Accelerator-Rich Architectures

EDA-ML: Graph Representation Learning Framework for Digital IC Design Automation

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