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Post Silicon Power/Performance Optimization in the Presence of Process Variations Using Individual Well-Adaptive Body Biasing

IEEE transactions on very large scale integration (VLSI) systems, 2007-03, Vol.15 (3), p.366-376

2007

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Characterization of Novel Microelectrode Geometries for Detection of Neurotransmitters

IEEE sensors journal, 2012-05, Vol.12 (5), p.1187-1192

2012

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CMOS optoelectronic components for clock distribution

Microelectronic engineering, 2010-10, Vol.87 (10), p.1838-1845

2010

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Γ (Gamma): A SaaS-enabled fast and accurate analog design System

Integration (Amsterdam), 2016-09, Vol.55, p.67-84

2016

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A VLSI architecture for video-object segmentation

IEEE transactions on circuits and systems for video technology, 2003-01, Vol.13 (1), p.83-96

2003

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A novel high-throughput method for table look-up based analog design automation

Integration (Amsterdam), 2016-01, Vol.52, p.168-181

2016

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A PVT-compensated capacitive sensor with sub-1fF sensitivity

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS), 2015, p.1-4

2015

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A low power frequency synthesizer for biosensor applications in the MedRadio band

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS), 2015, p.1-4

2015

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Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation

IEEE transactions on very large scale integration (VLSI) systems, 2003-10, Vol.11 (5), p.888-899

2003

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A practical automated timing and physical design implementation methodology for the synchronous asynchronous interface and multi-voltage domain in high-speed synthesis

Microprocessors and microsystems, 2016-09, Vol.45, p.241-252

2016

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Synthesis-based design and implementation methodology of high-speed, high-performing unit: L2 cache unit design

Integration (Amsterdam), 2015-03, Vol.49, p.125-136

2015

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Offset correction of low power, high precision op amp using digital assist for biomedical applications

2012 IEEE International Symposium on Circuits and Systems (ISCAS), 2012, p.850-853

2012

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Fully CMOS-Compatible On-Chip Optical Clock Distribution and Recovery

IEEE transactions on very large scale integration (VLSI) systems, 2010-10, Vol.18 (10), p.1385-1398

2010

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Low power integrated potentiostat design for μ electrodes with improved accuracy

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 2011, p.1-4

2011

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Rapid design space exploration using legacy design data and technology scaling trend

Integration (Amsterdam), 2010-04, Vol.43 (2), p.202-219

2010

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Assessing merged DRAM/Logic technology

Integration (Amsterdam), 1999, Vol.27 (2), p.179-194

1999

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Design of a capacitance sensor in 0.18um CMOS technology for biomedical application

2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), 2013, p.396-399

2013

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On the impact of on-chip inductance on signal nets under the influence of power grid noise

IEEE transactions on very large scale integration (VLSI) systems, 2005-03, Vol.13 (3), p.339-348

Chen, T.

2005

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Design target exploration for meeting time-to-market using pareto analysis

2008 IEEE International Symposium on Circuits and Systems (ISCAS), 2008, p.364-367

2008

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DDR5 Electrical Challenges in High-Speed Server Design

2023 Joint Asia-Pacific International Symposium on Electromagnetic Compatibility and International Conference on ElectroMagnetic Interference & Compatibility (APEMC/INCEMIC), 2023, p.1-4

2023

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Geometry Dependence of CMOS-Compatible, Polysilicon, Leaky-Mode Photodetectors

IEEE photonics technology letters, 2007-04, Vol.19 (7), p.513-515

2007

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Statistical timing analysis of coupled interconnects using quadratic delay-change characteristics

IEEE transactions on computer-aided design of integrated circuits and systems, 2004-12, Vol.23 (12), p.1677-1683

2004

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A sensitivity-based approach to analyzing signal delay uncertainty of coupled interconnects

IEEE transactions on computer-aided design of integrated circuits and systems, 2005-09, Vol.24 (9), p.1336-1346

2005

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Near-linear CMOS I/O driver with less sensitivity to process, voltage, and temperature variations

IEEE transactions on very large scale integration (VLSI) systems, 2004-11, Vol.12 (11), p.1253-1257

2004

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A VLSI architecture for real-time edge linking

IEEE transactions on pattern analysis and machine intelligence, 1999-01, Vol.21 (1), p.89-94

1999

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Post Silicon Power/Performance Optimization in the Presence of Process Variations Using Individual Well-Adaptive Body Biasing

Characterization of Novel Microelectrode Geometries for Detection of Neurotransmitters

CMOS optoelectronic components for clock distribution

Γ (Gamma): A SaaS-enabled fast and accurate analog design System

A VLSI architecture for video-object segmentation

A novel high-throughput method for table look-up based analog design automation

A PVT-compensated capacitive sensor with sub-1fF sensitivity

A low power frequency synthesizer for biosensor applications in the MedRadio band

Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation

A practical automated timing and physical design implementation methodology for the synchronous asynchronous interface and multi-voltage domain in high-speed synthesis

Synthesis-based design and implementation methodology of high-speed, high-performing unit: L2 cache unit design

Offset correction of low power, high precision op amp using digital assist for biomedical applications

Fully CMOS-Compatible On-Chip Optical Clock Distribution and Recovery

Low power integrated potentiostat design for μ electrodes with improved accuracy

Rapid design space exploration using legacy design data and technology scaling trend

Assessing merged DRAM/Logic technology

Design of a capacitance sensor in 0.18um CMOS technology for biomedical application

On the impact of on-chip inductance on signal nets under the influence of power grid noise

Design target exploration for meeting time-to-market using pareto analysis

DDR5 Electrical Challenges in High-Speed Server Design

Geometry Dependence of CMOS-Compatible, Polysilicon, Leaky-Mode Photodetectors

Statistical timing analysis of coupled interconnects using quadratic delay-change characteristics

A sensitivity-based approach to analyzing signal delay uncertainty of coupled interconnects

Near-linear CMOS I/O driver with less sensitivity to process, voltage, and temperature variations

A VLSI architecture for real-time edge linking

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