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LSTM-Based Hierarchical Denoising Network for Android Malware Detection

Security and communication networks, 2018-01, Vol.2018 (2018), p.1-18

2018

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Identifying Fake Accounts on Social Networks Based on Graph Analysis and Classification Algorithms

Security and communication networks, 2018-01, Vol.2018 (2018), p.1-8

2018

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Empirical Evaluation of Noise Influence on Supervised Machine Learning Algorithms Using Intrusion Detection Datasets

Security and communication networks, 2021-01, Vol.2021, p.1-28

2021

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Silence is Golden: A Source Location Privacy Scheme for Wireless Sensor Networks Based on Silent Nodes

Security and communication networks, 2022-11, Vol.2022, p.1-16

2022

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Attention-Guided Digital Adversarial Patches on Visual Detection

Security and communication networks, 2021, Vol.2021, p.1-11

2021

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A Mean Convolutional Layer for Intrusion Detection System

Security and communication networks, 2020, Vol.2020 (2020), p.1-16

2020

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Research on Lightweight Mutual Authentication for the Product Authorization Chain

Security and communication networks, 2021-09, Vol.2021, p.1-9

2021

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UPPGHA: Uniform Privacy Preservation Group Handover Authentication Mechanism for mMTC in LTE-A Networks

Security and communication networks, 2018-01, Vol.2018 (2018), p.1-16

2018

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An Active Controller Selection Scheme for Minimizing Packet-In Processing Latency in SDN

Security and communication networks, 2019, Vol.2019 (2019), p.1-11

2019

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A Second Preimage Attack on the XOR Hash Combiner

IET information security, 2024-03, Vol.2024, p.1-7

2024

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Bit-Sliced Implementation of SM4 and New Performance Records

IET information security, 2023-10, Vol.2023, p.1-10

2023

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A Survey of Secure Communications for Satellite Internet Based on Cryptography and Physical Layer Security

IET information security, 2023-10, Vol.2023, p.1-15

2023

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The Effect of the Primitive Irreducible Polynomial on the Quality of Cryptographic Properties of Block Ciphers

Security and communication networks, 2020-09, Vol.2020 (2020), p.1-14

2020

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Post Silicon Power/Performance Optimization in the Presence of Process Variations Using Individual Well-Adaptive Body Biasing

IEEE transactions on very large scale integration (VLSI) systems, 2007-03, Vol.15 (3), p.366-376

2007

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Γ (Gamma): A SaaS-enabled fast and accurate analog design System

Integration (Amsterdam), 2016-09, Vol.55, p.67-84

2016

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A novel high-throughput method for table look-up based analog design automation

Integration (Amsterdam), 2016-01, Vol.52, p.168-181

2016

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Brain Tumor Segmentation (BraTS) Challenge Short Paper: Improving Three-Dimensional Brain Tumor Segmentation Using SegResnet and Hybrid Boundary-Dice Loss

Brainlesion: Glioma, Multiple Sclerosis, Stroke and Traumatic Brain Injuries, p.334-344

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Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation

IEEE transactions on very large scale integration (VLSI) systems, 2003-10, Vol.11 (5), p.888-899

2003

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A 2nd Order CMOS Sigma-Delta Modulator Design Suitable for Low-Power Biosensor Applications

Biomedical Engineering Systems and Technologies, p.3-12

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A practical automated timing and physical design implementation methodology for the synchronous asynchronous interface and multi-voltage domain in high-speed synthesis

Microprocessors and microsystems, 2016-09, Vol.45, p.241-252

2016

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Synthesis-based design and implementation methodology of high-speed, high-performing unit: L2 cache unit design

Integration (Amsterdam), 2015-03, Vol.49, p.125-136

2015

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Cyberterrorism: Understanding, Assessment, and Response

2014, 2014

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Fully CMOS-Compatible On-Chip Optical Clock Distribution and Recovery

IEEE transactions on very large scale integration (VLSI) systems, 2010-10, Vol.18 (10), p.1385-1398

2010

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Low power integrated potentiostat design for μ electrodes with improved accuracy

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 2011, p.1-4

2011

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Rapid design space exploration using legacy design data and technology scaling trend

Integration (Amsterdam), 2010-04, Vol.43 (2), p.202-219

2010

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LSTM-Based Hierarchical Denoising Network for Android Malware Detection

Identifying Fake Accounts on Social Networks Based on Graph Analysis and Classification Algorithms

Empirical Evaluation of Noise Influence on Supervised Machine Learning Algorithms Using Intrusion Detection Datasets

Silence is Golden: A Source Location Privacy Scheme for Wireless Sensor Networks Based on Silent Nodes

Attention-Guided Digital Adversarial Patches on Visual Detection

A Mean Convolutional Layer for Intrusion Detection System

Research on Lightweight Mutual Authentication for the Product Authorization Chain

UPPGHA: Uniform Privacy Preservation Group Handover Authentication Mechanism for mMTC in LTE-A Networks

An Active Controller Selection Scheme for Minimizing Packet-In Processing Latency in SDN

A Second Preimage Attack on the XOR Hash Combiner

Bit-Sliced Implementation of SM4 and New Performance Records

A Survey of Secure Communications for Satellite Internet Based on Cryptography and Physical Layer Security

The Effect of the Primitive Irreducible Polynomial on the Quality of Cryptographic Properties of Block Ciphers

Post Silicon Power/Performance Optimization in the Presence of Process Variations Using Individual Well-Adaptive Body Biasing

Γ (Gamma): A SaaS-enabled fast and accurate analog design System

A novel high-throughput method for table look-up based analog design automation

Brain Tumor Segmentation (BraTS) Challenge Short Paper: Improving Three-Dimensional Brain Tumor Segmentation Using SegResnet and Hybrid Boundary-Dice Loss

Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation

A 2nd Order CMOS Sigma-Delta Modulator Design Suitable for Low-Power Biosensor Applications

A practical automated timing and physical design implementation methodology for the synchronous asynchronous interface and multi-voltage domain in high-speed synthesis

Synthesis-based design and implementation methodology of high-speed, high-performing unit: L2 cache unit design

Cyberterrorism: Understanding, Assessment, and Response

Fully CMOS-Compatible On-Chip Optical Clock Distribution and Recovery

Low power integrated potentiostat design for μ electrodes with improved accuracy

Rapid design space exploration using legacy design data and technology scaling trend

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