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Epidermal thymic stromal lymphopoietin predicts the development of atopic dermatitis during infancy

Journal of allergy and clinical immunology, 2016-04, Vol.137 (4), p.1282-1285.e4

2016

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8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology

IEEE journal of solid-state circuits, 2010-01, Vol.45 (1), p.111-119

2010

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A 5.8-Gb/s Adaptive Integrating Duobinary DFE Receiver for Multi-Drop Memory Interface

IEEE journal of solid-state circuits, 2017-06, Vol.52 (6), p.1563-1575

2017

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Fast Output Voltage-Regulated PWM Buck Converter With an Adaptive Ramp Amplitude Control

IEEE transactions on circuits and systems. II, Express briefs, 2013-10, Vol.60 (10), p.712-716

2013

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A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface

IEEE journal of solid-state circuits, 2012-04, Vol.47 (4), p.981-989

2012

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Simultaneous Reverse Body and Negative Word-Line Biasing Control Scheme for Leakage Reduction of DRAM

IEEE journal of solid-state circuits, 2011-10, Vol.46 (10), p.2396-2405

2011

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Adaptive Multi-Pulse Program Scheme Based on Tunneling Speed Classification for Next Generation Multi-Bit/Cell NAND FLASH

IEEE journal of solid-state circuits, 2013-04, Vol.48 (4), p.948-959

2013

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A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme

IEEE journal of solid-state circuits, 2009-08, Vol.44 (8), p.2222-2232

2009

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CMOS Charge Pump With Transfer Blocking Technique for No Reversion Loss and Relaxed Clock Timing Restriction

IEEE transactions on circuits and systems. II, Express briefs, 2009-01, Vol.56 (1), p.11-15

2009

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A Digitally Controlled Oscillator With Wide Frequency Range and Low Supply Sensitivity

IEEE transactions on circuits and systems. II, Express briefs, 2011-10, Vol.58 (10), p.632-636

2011

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Conditional-capture flip-flop for statistical power reduction

IEEE journal of solid-state circuits, 2001-08, Vol.36 (8), p.1263-1271

2001

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A 0.13- \mu m CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN

IEEE journal of solid-state circuits, 2009-11, Vol.44 (11), p.3146-3162

2009

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An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion

IEEE journal of solid-state circuits, 2008-01, Vol.43 (1), p.121-131, Article 121

2008

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A 31 ns Random Cycle VCAT-Based 4F ^ DRAM With Manufacturability and Enhanced Cell Efficiency

IEEE journal of solid-state circuits, 2010-04, Vol.45 (4), p.880-888

2010

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A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction

IEEE journal of solid-state circuits, 2011-01, Vol.46 (1), p.107-118

2011

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P‐200: N‐type Host Derived from Phenyl‐Triazine Moiety for Low Driving Voltage in Blue Phosphorescent Organic Light‐Emitting Diodes

SID International Symposium Digest of technical papers, 2024-06, Vol.55 (1), p.2147-2149

2024

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A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking

IEEE journal of solid-state circuits, 2012, Vol.47 (1), p.107-116

2012

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Adaptive Digital Background Gain Mismatch Calibration for Multi-lane High-speed Serial Links

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2015, 15(1), 61, pp.96-100

2015

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A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces

IEEE journal of solid-state circuits, 2009-05, Vol.44 (5), p.1522-1530

2009

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A line inversion-based stepwise data driving for low-power mobile TFT-LCDs

IEEE transactions on consumer electronics, 2010-05, Vol.56 (2), p.1002-1009

2010

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Low-Power CMOS Synchronous Counter With Clock Gating Embedded Into Carry Propagation

IEEE transactions on circuits and systems. II, Express briefs, 2009-08, Vol.56 (8), p.649-653

2009

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High-Speed Low-Power Boosted Level Converters for Dual Supply Systems

IEICE transactions on electronics, 2012, Vol.E95.C (11), p.1824-1826

2012

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A DFE Receiver With Equalized VREF for Multidrop Single-Ended Signaling

IEEE transactions on circuits and systems. II, Express briefs, 2013-07, Vol.60 (7), p.412-416

2013

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CMOS Charge Pump With No Reversion Loss and Enhanced Drivability

IEEE transactions on very large scale integration (VLSI) systems, 2014-06, Vol.22 (6), p.1441-1445

2014

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CMOS temperature sensor with ring oscillator for mobile DRAM self-refresh control

2008 IEEE International Symposium on Circuits and Systems, 2008, p.3094-3097

2008

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Epidermal thymic stromal lymphopoietin predicts the development of atopic dermatitis during infancy

8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology

A 5.8-Gb/s Adaptive Integrating Duobinary DFE Receiver for Multi-Drop Memory Interface

Fast Output Voltage-Regulated PWM Buck Converter With an Adaptive Ramp Amplitude Control

A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface

Simultaneous Reverse Body and Negative Word-Line Biasing Control Scheme for Leakage Reduction of DRAM

Adaptive Multi-Pulse Program Scheme Based on Tunneling Speed Classification for Next Generation Multi-Bit/Cell NAND FLASH

A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme

CMOS Charge Pump With Transfer Blocking Technique for No Reversion Loss and Relaxed Clock Timing Restriction

A Digitally Controlled Oscillator With Wide Frequency Range and Low Supply Sensitivity

Conditional-capture flip-flop for statistical power reduction

A 0.13- \mu m CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion

A 31 ns Random Cycle VCAT-Based 4F ^ DRAM With Manufacturability and Enhanced Cell Efficiency

A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction

P‐200: N‐type Host Derived from Phenyl‐Triazine Moiety for Low Driving Voltage in Blue Phosphorescent Organic Light‐Emitting Diodes

A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking

Adaptive Digital Background Gain Mismatch Calibration for Multi-lane High-speed Serial Links

A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces

A line inversion-based stepwise data driving for low-power mobile TFT-LCDs

Low-Power CMOS Synchronous Counter With Clock Gating Embedded Into Carry Propagation

High-Speed Low-Power Boosted Level Converters for Dual Supply Systems

A DFE Receiver With Equalized VREF for Multidrop Single-Ended Signaling

CMOS Charge Pump With No Reversion Loss and Enhanced Drivability

CMOS temperature sensor with ring oscillator for mobile DRAM self-refresh control

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