UB Paderborn / Katalog / Suche / in CDI

Emission charge and liner shipping network configuration – An economic investigation of the Asia-Europe route

Transportation research. Part A, Policy and practice, 2018-04, Vol.110, p.291-305

2018

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Efficient three-dimensional extraction based on static and full-wave layered Green's functions

Proceedings - ACM IEEE Design Automation Conference, 1998

1998

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Planar clock routing for high performance chip and package co-design

IEEE transactions on very large scale integration (VLSI) systems, 1996-06, Vol.4 (2), p.210-226

1996

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Useful-skew clock routing with gate sizing for low power design

Annual ACM IEEE Design Automation Conference: Proceedings of the 33rd annual conference on Design automation; 03-07 June 1996, 1996, p.383-388

1996

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Capture partial reluctance more efficiently for complex interconnect structure

2004 IEEE MTT-S International Microwave Symposium Digest (IEEE Cat. No.04CH37535), 2004, Vol.3, p.1389-1392 Vol.3

2004

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Buffer insertion and sizing under process variations for low power clock distribution

Annual ACM IEEE Design Automation Conference: Proceedings of the 32nd ACM/IEEE conference on Design automation; 12-16 June 1995, 1995, p.491-496

1995

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High-performance datapath implementation on Field-Programmable Multi-Chip Module (FPMCM)

Field-Programmable Logic Architectures, Synthesis and Applications, 2005, p.373-383

2005

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Capture high-frequency partial inductance more accurately by gauss quadrature integration with skin-effect model

IEEE transactions on microwave theory and techniques, 2006-03, Vol.54 (3), p.1287-1294

2006

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Arbitrary rectilinear block packing based on sequence pair

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287), 1998, p.259-266

1998

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Chip parasitic extraction and signal integrity verification (extended abstract)

Annual ACM IEEE Design Automation Conference: Proceedings of the 34th annual conference on Design automation; 09-13 June 1997, 1997, p.717-719

Dai, Wayne W.-M.

1997

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Yield-preferred via insertion based on novel geotopological technology

Proceedings of the 2006 Asia and South Pacific Design Automation Conference, 2006, p.730-735

2006

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Area minimization of power distribution network using efficient nonlinear programming techniques

IEEE transactions on computer-aided design of integrated circuits and systems, 2004-07, Vol.23 (7), p.1086-1094

2004

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Partial reluctance based circuit simulation is efficient and stable

Proceedings of the 2005 Asia and South Pacific Design Automation Conference, 2005, p.483-488

2005

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Fast parameters extraction of general three-dimension interconnects using geometry independent measured equation of invariance

Annual ACM IEEE Design Automation Conference: Proceedings of the 33rd annual conference on Design automation; 03-07 June 1996, 1996, p.371-376

1996

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TEG: a new post-layout optimization method

IEEE transactions on computer-aided design of integrated circuits and systems, 2003-04, Vol.22 (4), p.446-456

2003

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High-speed clock network sizing optimization based on distributed RC and lossy RLC interconnect models

IEEE transactions on computer-aided design of integrated circuits and systems, 1996-09, Vol.15 (9), p.1106-1118

1996

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TEG: a new post-layout optimization method

International Symposium on Physical Design: Proceedings of the 2002 international symposium on Physical design; 07-10 Apr. 2002, 2002, p.62-67

2002

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Fast parameter extraction of general interconnects using geometry independent measured equation of invariance

IEEE transactions on microwave theory and techniques, 1997-05, Vol.45 (5), p.827-836

1997

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Post-route optimization for improved yield using a rubber-band wiring model

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD), 1997, p.700-706

1997

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Modeling and analysis of integrated spiral inductors for RF system-in-package

Proceedings of the 2000 Asia and South Pacific Design Automation Conference, 2000, p.211-216

2000

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Routability of a rubber-band sketch

28th ACM/IEEE Design Automation Conference, 1991, p.45-48

1991

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Delay bounded buffered tree construction for timing driven floorplanning

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD), 1997, p.707-712

1997

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S-parameter based macro model of distributed-lumped networks using exponentially decayed polynomial function

Annual ACM IEEE Design Automation Conference: Proceedings of the 30th international conference on Design automation; 14-18 June 1993, 1993, p.726-731

1993

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Crosstalk noise estimation for noise management

Annual ACM IEEE Design Automation Conference: Proceedings of the 39th conference on Design automation : New Orleans, Louisiana, USA; 10-14 June 2002, 2002, p.659-664

2002

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A novel dimension-reduction technique for the capacitance extraction of 3-D VLSI interconnects

IEEE transactions on microwave theory and techniques, 1998-08, Vol.46 (8), p.1037-1044

1998

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Emission charge and liner shipping network configuration – An economic investigation of the Asia-Europe route

Efficient three-dimensional extraction based on static and full-wave layered Green's functions

Planar clock routing for high performance chip and package co-design

Useful-skew clock routing with gate sizing for low power design

Capture partial reluctance more efficiently for complex interconnect structure

Buffer insertion and sizing under process variations for low power clock distribution

High-performance datapath implementation on Field-Programmable Multi-Chip Module (FPMCM)

Capture high-frequency partial inductance more accurately by gauss quadrature integration with skin-effect model

Arbitrary rectilinear block packing based on sequence pair

Chip parasitic extraction and signal integrity verification (extended abstract)

Yield-preferred via insertion based on novel geotopological technology

Area minimization of power distribution network using efficient nonlinear programming techniques

Partial reluctance based circuit simulation is efficient and stable

Fast parameters extraction of general three-dimension interconnects using geometry independent measured equation of invariance

TEG: a new post-layout optimization method

High-speed clock network sizing optimization based on distributed RC and lossy RLC interconnect models

TEG: a new post-layout optimization method

Fast parameter extraction of general interconnects using geometry independent measured equation of invariance

Post-route optimization for improved yield using a rubber-band wiring model

Modeling and analysis of integrated spiral inductors for RF system-in-package

Routability of a rubber-band sketch

Delay bounded buffered tree construction for timing driven floorplanning

S-parameter based macro model of distributed-lumped networks using exponentially decayed polynomial function

Crosstalk noise estimation for noise management

A novel dimension-reduction technique for the capacitance extraction of 3-D VLSI interconnects

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