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Compact Analytical Model for Trap-Related Low Frequency Noise in Junctionless Transistors

ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC), 2019, p.194-197

2019

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Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors

ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC), 2021, p.223-226

2021

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Evaluation and implementation of High-Dimensionnal Computing for gesture recognition using sEMG signals

2024 International Conference on Control, Automation and Diagnosis (ICCAD), 2024, p.1-6

2024

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Scaling-aware TCAD Parameter Extraction Methodology for Mobility Prediction in Tri-gate Nanowire Transistors

2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2019, p.1-4

2019

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A new method for junctionless transistors parameters extraction

2017 47th European Solid-State Device Research Conference (ESSDERC), 2017, p.66-69

2017

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IEEE_Xplore

New insight on the geometry dependence of BTI in 3D technologies based on experiments and modeling

2017 Symposium on VLSI Technology, 2017, p.T134-T135

2017

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From devices to circuits: modelling the performance of 5nm nanosheets

2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2019, p.1-4

2019

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Size-dependent carrier mobilities in rectangular silicon nanowire devices

2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2016, p.257-260

2016

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IEEE_Xplore

Analog performance of strained SOI nanowires down to 10K

2016 46th European Solid-State Device Research Conference (ESSDERC), 2016, p.222-225

2016

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IEEE_Xplore

Statistical low-frequency noise characterization in sub-15 nm Si/SiGe nanowire Trigate pMOSFETs

2017 International Conference of Microelectronic Test Structures (ICMTS), 2017, p.1-5

2017

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Back-gate effects and detailed characterization of junctionless transistor

2015 45th European Solid State Device Research Conference (ESSDERC), 2015, p.282-285

2015

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Detection of the first charged states in ultrasmall Si single-hole transistor using dual-channel radio frequency reflectometry

72nd Device Research Conference, 2014, p.83-84

2014

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IEEE_Xplore

High and low-field contact resistances in trigate devices in a Non-Equilibrium Green's Functions framework

2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2016, p.291-294

2016

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IEEE_Xplore

Electrical Characterization of Ω-Gate Nanowire MOSFETs Down to Cryogenic Temperatures

2023 37th Symposium on Microelectronics Technology and Devices (SBMicro), 2023, p.1-4

2023

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Low-field Mobility Degradation Factors Temperature Dependence in Two-level Stacked Nanowire MOSFETs from 120K to 400K

2023 37th Symposium on Microelectronics Technology and Devices (SBMicro), 2023, p.1-4

2023

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Drain Current Variability in 2-levels Stacked Nanowire Gate All Around P-type Field Effect Transistors

2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 2023, p.1-3

2023

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Extraction of Drain Current Variability Components in Junctionless Nanowire Transistors

2023 International Conference on Noise and Fluctuations (ICNF), 2023, p.1-4

2023

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A wigner function-based determinist method for the simulation of quantum transport in silicon nanowire transistors

2011 International Conference on Simulation of Semiconductor Processes and Devices, 2011, p.75-78

2011

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IEEE_Xplore

High-Resolution DNA Binding Kinetics Measurements with Double Gate FD-SOI Transistors

2022 International Electron Devices Meeting (IEDM), 2022, p.24.2.1-24.2.4

2022

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IEEE_Xplore

Experimental Comparison of Junctionless and Inversion-Mode Nanowire MOSFETs Electrical Properties at High Temperatures

2022 36th Symposium on Microelectronics Technology (SBMICRO), 2022, p.1-4

2022

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Analysis of the Gate-Induced Drain Leakage of SOI Nanowire and Nanosheet MOS Transistors at High Temperatures

2022 IEEE Latin American Electron Devices Conference (LAEDC), 2022, p.1-4

2022

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Disruptive approaches towards Energy Efficient VLSI Technologies

2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT), 2023, p.1-2

2023

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Analysis of Variability in Transconductance and Mobility of Nanowire Transistors

2022 36th Symposium on Microelectronics Technology (SBMICRO), 2022, p.1-4

2022

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Evaluation of Analog Characteristics of n-Type Vertically Stacked Nanowires

2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2020, p.1-4

2020

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IEEE_Xplore

An Experimental Evaluation of Fin Width and Low-Temperature Influence on GIDL in Stacked SOI Nanowires

2022 IEEE 15th Workshop on Low Temperature Electronics (WOLTE), 2022, p.1-4

2022

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Compact Analytical Model for Trap-Related Low Frequency Noise in Junctionless Transistors

Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors

Evaluation and implementation of High-Dimensionnal Computing for gesture recognition using sEMG signals

Scaling-aware TCAD Parameter Extraction Methodology for Mobility Prediction in Tri-gate Nanowire Transistors

A new method for junctionless transistors parameters extraction

New insight on the geometry dependence of BTI in 3D technologies based on experiments and modeling

From devices to circuits: modelling the performance of 5nm nanosheets

Size-dependent carrier mobilities in rectangular silicon nanowire devices

Analog performance of strained SOI nanowires down to 10K

Statistical low-frequency noise characterization in sub-15 nm Si/SiGe nanowire Trigate pMOSFETs

Back-gate effects and detailed characterization of junctionless transistor

Detection of the first charged states in ultrasmall Si single-hole transistor using dual-channel radio frequency reflectometry

High and low-field contact resistances in trigate devices in a Non-Equilibrium Green's Functions framework

Electrical Characterization of Ω-Gate Nanowire MOSFETs Down to Cryogenic Temperatures

Low-field Mobility Degradation Factors Temperature Dependence in Two-level Stacked Nanowire MOSFETs from 120K to 400K

Drain Current Variability in 2-levels Stacked Nanowire Gate All Around P-type Field Effect Transistors

Extraction of Drain Current Variability Components in Junctionless Nanowire Transistors

A wigner function-based determinist method for the simulation of quantum transport in silicon nanowire transistors

High-Resolution DNA Binding Kinetics Measurements with Double Gate FD-SOI Transistors

Experimental Comparison of Junctionless and Inversion-Mode Nanowire MOSFETs Electrical Properties at High Temperatures

Analysis of the Gate-Induced Drain Leakage of SOI Nanowire and Nanosheet MOS Transistors at High Temperatures

Disruptive approaches towards Energy Efficient VLSI Technologies

Analysis of Variability in Transconductance and Mobility of Nanowire Transistors

Evaluation of Analog Characteristics of n-Type Vertically Stacked Nanowires

An Experimental Evaluation of Fin Width and Low-Temperature Influence on GIDL in Stacked SOI Nanowires

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